LabVIEW FPGA Master and FPGA EtherCAT Slave

[carlos_camargo]

Hi All,

I'm using LV 2019 with a cRIO-9074 as master and an NI-9144 as a slave, both are being programmed in FPGA mode.

Is there a way to communicate between them directly?

This thread states that communication between the master and slave requires relaying data through and RT program:

https://forums.ni.com/t5/LabVIEW/Communication-between-the-FPGA-Master-and-the-9144-FPGA/m-p/2934804...

Is that correct? 

Because if it is, it means I need to abandon the determinism and reliability of FPGA code and run any signals through the RT code.

I also then have to produce another layer of Host code, at the RT level.  My goal is to only create Host code at the Windows Level.

I'm hoping to find there's a way to communicate directly between cRIO-9074 FPGA and NI-9144 FPGA code.

Thanks,

 C

[ZYOng]

That's correct. NI does not provide support EtherCAT on the FPGA level, only on the RT level.

EtherCAT is a deterministic data communication protocol over Ethernet packets. At the RT level, the data exchange is deterministic but capped at 1 kHz by the scan engine on cRIO-9074. 

Unfortunately, RT code is necessary for your use case.

[carlos_camargo]

Thanks.

That's unfortunate, I was hoping there was a solution similar to the PXI-MXI interface where the I/O is transparently available regardless of location.

I'm not even concerned about determinism really, rather just annoyed at having to route data through the RT, which I was hoping to avoid entirely.

[ZYOng · Accepted solution]

If you use a non-EtherCAT Ethernet expansion RIO chassis (NI-9146/7/8/9), you can access the RIO server directly from the Windows PC (See Setup Guide for Ethernet RIO Expansion Chassis), but no data exchange between RIO chassis and without deterministic communication.

Similarly, if you can abandon the data communication between RIO chassis, you still use only the Windows host VI.

• Use the Open FPGA VI Ref VI on Windows to access the RIO server of cRIO-9074.
• Use Windows EtherCAT Library for LabVIEW to communicate with NI-9144.

PXI-MXI is based on PCI expansion. It is essentially the addition of more devices to the same PC.

cRIO does not have the same architecture. The straightforward way would be using the provided Ethernet or EtherCAT communication, which have to be routed on RT level.

Expansion I/O for LabVIEW RIO Systems: An In-Depth Comparison

There are some more complicated way as well.

• You could install cRIO OPIF 20MBit/s on each RIO chassis and program the FPGA to exchange the data directly.
• Or install any NI Digital IO module on each RIO chassis and implement NI SPI IP Toolkit for LabVIEW on FPGA to exchange data over external wiring.

[carlos_camargo]

Thanks for the clear answer and helpful suggestions.