02-06-2012 12:50 PM
Dear All,
I just got a NI PCIe-7852R FPGA board. I'm new to FPGA and am just trying a few simple things. I've made an FPGA derived clock running at 4MHz and am using a single cycle timed loop with this clock to output a square wave. I've attached a screen shot of the program I've compiled to the target and the VI running on the host computer. Nothing fancy. But I don't get anything close to a clean high frequency square wave output. Rather I get a ~12Hz ugly square wave out (see attached o-scope screen shots). Can someone tell me what I'm doing wrong? I've also tried both high impedance and 50 ohm termination. I haven't found which is correct in the manual for this board.
Thanks,
Ed
02-07-2012 08:04 AM - edited 02-07-2012 08:05 AM
Okay, sorry about this post. When I set the time scale on my o-scope to the appropriate order of magnitude I do see a periodic signal that is the correct frequency. My mistake. However, it doesn't look good. Not really square, more like a poor approximation. Any idea what the rise/fall time on the DIO lines are?
02-07-2012 05:26 PM
Hi Edward,
The minimum output pulse width on the 7852R card is 12.5ns. Thus, the DIO rise/fall time are lower than 12,5ns. Have you tried running one of our standard examples? I've attached one of them to this post.Can you run this example an post your results?