LabVIEW FPGA compile timing error

[paul o]

I am in the final stages of building an end-to-end speech recognition system on a PXI-7833R and am running into a timing error when compiling the full system.  I posted about a similar related issue a couple days ago.  Basically, each sub-vi of the system compiles properly, but when together there is a timing error reported after it compiles.  I have been pipelining where possible, but it is difficult to know where in the code the timing errors are occurring because of the complexity of the system.  There are three ways I could theoretically fix or work around the problem assuming I could do them in LabVIEW:

1) Trace the location of the errors from the compiler output to the VI
2) Adjust compiler flags to optimize some efforts to fix the error
3) Tell the compiler to allow top level clock rates of less than 40MHz

Are any of these possible?  I am attaching pictures of the main VI.  The false portion of all the case structures is empty.  Thank you for your help.

~Paul

[Eli_S]

Hi Paul O,

First of all, I did not see any pipelining in the picture you posted, I guess you must have done it in the SubVi's. As far as the three options you suggested, unfortunatelly you cannot do any of them in LabVIEW. I would suggest disabling all loops except for one and narrow down that way which loop is failing timing.

Some things I can suggest are that you may be using to many multimplications of large numbers, which usually take more than an single cycle. Break down the multiplications to fixed-point, which will allow you to pipeline those as well.