LabVIEW and Verilog RTL

[bob_miller]

Having spent enough time developing applications in LabVIEW to get
nicely addicted to the programming environment, I have spent some
time pondering whether LabVIEW can or could be cajoled into creating
structures analogous to those developed in Verilog RTL modules for
synthesis into logic. Such modules are (or should be) highly structured,
with a parallel execution model, generally event-driven (LabVIEW might
have some deficiencies here), and could greatly benefit from a practical
graphical development environment, particularly since such designs are
ideally constructed with a constant view towards the dataflow graph that
drives the connectivity of the hardware implementation, something which
I think LabVIEW could be very good at.

Now LabVIEW has no "back end spigot" to spit out, say, synthesizable
Verilog/VHDL (although it *can* map a VI to
highly constrained gates in the FPGA module). So my dream of a LabVIEW
RTL Develoment environment is a long ways off. But I wonder if anyone
out there has spent any time building Labview analogues to typical
Verilog RTL modules. If so I'd love to hear what you learned.

One of the biggest questions in my mind is how to model the Verilog
event structure, e.g.:

"always @( or or...)begin...(do stuff)...end"

or

"always @(posedge)begin...end", etc.

These constructs look tantalizingly similar to the LabVIEW programmatic
event structure, though the "when this variable or this variable changes:"
or the "when this variable transitions true: fire the event" would have to
be explicitly coded versus having these ready-made functions already built in
the LabVIEW event structure.

The concept of delay (verilog "#") and timescale would also need to find an
appropriate dual in the LabVIEW world. Shift registers and feedback nodes
look something like this, but are not the obvious mappings that other items
like case and while structures are.

Anyone out there thought about this? I am exploring trying to LabVIEW analogue
of a couple of basic Verilog modules running in such a way that the dataflow
timing is generally matched (and of course the two machines function in
generally the same way).

Its probably only a daydream...;-)

Bob

[P. Jack]

I think LabVIEW FPGA converts SCTL to process block (or in Verilog, always). To make a synchronous application, you just have to make all of the SCTLs operate at the same clock source. But I don't know which edge, but this is unncessary because LabVIEW handles that. Doing that, I can call it graphical RTL (graphical HDL in RTL abstraction, actually).

What I really wanted is to have one SCTL on every subVI and make the input and output of that subVI analogous to nets. Also, I would want a loop that is not dependent on a clock edge instead dependent on a value change in any of its input. Like the combinational logic modelling using an always block. And much of what I have wanted is to see the RTL representation of my graphical RTL. This is a diagram expressed in DFF, AND, OR gates, etc.

On the other hand, anything else is behavioral. Then, I can make a simulation of my graphical RTL before loading it to the FPGA module. (I do not how the emulator works, I do not have the luxury of time to know what it can do.)