Labview FPGA: Better definition of DMA FIFO ports. Also, what happens when FIFO is full?

[TomC_NGC]

I'm using a DMA-to-Host FIFO in Labview FPGA.

On the Write side: 

There are a couple of ports, Timeout and Timed Out, that I'm not sure about.

From what I can see, Timeout is useless in a Timed Loop.

Timed Out seems to indicate that data was lost.

Does the FIFO cease to function at this point, or will it continue to work normally once data is popped out of the FIFO by the Host?

On the Read Side:

There is a port called Timeout, description below. I have no idea what it does. What does "timing out" mean on the read side of a FIFO? Does it mean there is no data? That seems strange.

Timeout (ms) specifies the number of milliseconds the Invoke Method function waits before timing out. The default is 5000 milliseconds. Set this parameter to –1 if you want the Invoke Method function to wait indefinitely for the number of elements.

[nathand]

The "Timeout" input sets how long the function will wait for the FIFO function to complete (either inserting or removing data).  If there's no room in the FIFO to add data, or not enough data available to be removed, the "Timed Out" output will be true.  If a timeout occurs while writing, data will be lost, but the FIFO will accept new data as soon as there's space available.  None of this should be related to timed loops, as a timed loop does not dictate timing of anything occurring inside of it.  If your FIFO timeout is longer than your timed loop period, and the FIFO has to wait for that timeout, your timed loop will run late.