Labview FPGA encoder reading

[belmaalma]

hello,

I an new in LabVIEW FPGA programing so I would appreciate any help. I am using sb-rio 9636 card and optocoupler for speed messaurment of DC motor. I have conected everyting right and the sensor is giving me date. But messauring the speed the oscilations of sensor data are huge. I am not changing the speed and motor continiousliy is rotating in the same speed but data are not the same. For example im 12 V that is the max speed motor schould rotate in 6500 rpm/min but in one second it is showing 6500 and in the other 5500 rpm/min.  think that there is not problem in the code but that the messaurment are not reliable. I will put my code. I need to know is there anz other way to do encoder readings.

Thank you

[Spex]

I don't see anything in your loop that guarantees the timing of your sampling of the digital encoder pulses.  It appears you expect that loop to run at 1MHz based on the uS unit label on your time of flight indicator.

Because you are using front panel indicators for some of your calculation variables, I can't see all the numbers going into your calculations.

How much variance do you see in the time of flight measurement on your front panel?  You must remember that you are making measurements in whole integers of uS.  How much change in the RPM calculation do you see if the uS measurement drifts by 1 uS?

If the impact of 1uS change in pulse to pulse measurement has a big impact on your calculation, then you will need to adjust your algorithm to get a more precise measure of the time of flight.

Some ideas:

1. The faster your sampling loop runs, the more likely you will sample the signal right after the pulse transistion.  Consider using a Single-Cycle Timed Loop to sample at speeds in the 40MHz (25ns period) range.  This will give you more precision.  One risk I can't rule out in your existing code is that you may be sampling slow enough that in some cases you miss a pulse completely.  If you want to ensure that you do not miss any pulse edged, then you must ensure that the loop is sampling at least 2x the frequency of your pulse train, assuming the pulses have a clean 50% duty cycle. If that duty cycle is not 50%, then the maximum sampling period must be shorter than the shortest pulse you expect.
2. Rather than measuring the time difference from pulse to pulse, measure the time of 10 pulses, or 1000 pulses, or some other larger number. This averages a larger number of pulses so that the difference of 1us resolution has less impact on the calculated measurement.

[belmaalma]

Thank you on your fast replay.  I considered everything that you sad. And I know that I must ensure that the loop is sampling at least 2x the frequency of your pulse train. If if replace while loop with timed loop with its clok  rate 40 MHz it will set sampling rate at 0,25 ns, am right? You asked me about time variance, so according to mesaurments it is between 100 and 200 us and that changes rpm at least 500.  Also I wanted to ask if I want to put other while loops in the same  Block Diagram do I have to set it in the same clok rate or it can be different? 

[Spex]

If you sample in a 40MHz Timed Loop, then yes, the period between each sample is 25ns.  

To see the measurements for Time of Flight jump that signifcantly (between 100 and 200 uS) would indicate to me that the while loop you currently have is samping too slowly, giving a course estimate of the time of flight. At the expected speed of 6500 RPM, what is the calculated theoretical time of flight between pulses?

I recommend defining the mathematical expectations you have for measurement precision and speed (sample rate), and then calcluating the actual measurement performance needed to acheive that precision.  Then you can confidently set a loop speed/measurement period that gives you reliable data, rather than just coding and adjusting until things look right.  The code and adjust method often works for LabVIEW, but when programming an FPGA, the time to compile can make this process of adjusting very slow.  

You can put many loops on the block diagram, and they can run independently.  All of the loops will share the same top level clock, but a while loop will execute slower than a timed loop of the same FPGA clock frequency.  This is because a timed loop runs in 1 clock period, but a while loop executes in multiple clock periods, dependant on how much code is in the while loop.

[belmaalma]

Once again thank you on your replay. I tried to change while loop in timed loop and now reading are more precise and I have less deviations. I wil ask my professor are this deviations acceptable, and if they are I will not change nothing more.