Loop Rates not adhered to while Emulating FPGA vi

[--thatguy]

I have two single cycle timed loops, one running at 50MHz and the other running at 100MHz.

When I emulate, I don't expect the loops to run at the requested rates, but I'd expect the 100MHz loop to run roughly twice as fast as the 50MHz loop.

Actually I see the 50MHz loop running faster?

Is this expected behavior?

[Christian Mergl]

The emulator is only for testing of the semantics, not of the timing behaviour.

Christian