Loop Speed Fluctuations FPGA

[omkara2233]

Hello,

I am sending model data from real time target to R series FPGA over DMA FIFO using Array. FPGA vi have for loop inside while loop to get back values from array. But I am seeing while loop speed fluctuations between 10 K to 65 K ticks as shown below. I am not sure if this is because of for loop or DMA FIFO. Any help on it is much appreciated.

Amplitude in Tick

[GerdW]

Hi omkara,

that is a nice image of a part of your frontpanel.

But I guess it is not the source of your problem - instead the problem should be in your code (aka VI).

Why don't you attach your VI(s) when you want help with it?

[Terry_ALE]

Can you post pictures of your FPGA code?

Variable tick count could mean you are using a regular loop and not a single cycled timed loop (SCTL).

[omkara2233]

Sorry, I have added FPGA VI in my original post but for some reason I don't see it . Here is the screen shot.For loop inside while loop

[RavensFan]

As Terry said, that is a regular while loop and not a single cycle timed loop.  You should use loops with blue borders in the FPGA.

Also, you have an unnecessary number of Index Arrays.  And you don't need those constants.

Delete all but the top one, drag the bottom border downward and you'll have more outputs.  By default they will be index 0, 1, 2, ..... without having to wire up any index constants.

[omkara2233]

I made changes as you suggested and replaced while loop with single cycled timed loop. During compilation I got following error.

Error -61003 occurred at

Possible reason(s):

LabVIEW FPGA: You cannot include this function in a For Loop when the For Loop is inside a single-cycle Timed Loop.

[BertMcMahan]

You're also reading from a buffer with infinite timeout, so it could be your FPGA code is totally fine but the buffer is being filled at a variable rate.

[RavensFan]

Move the indicator out of the for loop.

[omkara2233]

Yes, on my write and read DMA fifo timeout set to -1 (No timeout). I am setting and monitoring following DMA parameters.

Requested depth set to = 10 (For 10 channels)

Actual Depth = 512

Empty elements Remaining = 502

Empty elements given above is constant at every iteration. From this I deduced my buffer is not overflowing, but I am not positive about this approach.

How can I make sure my buffer is not over flowing?

[Terry_ALE]

You could check the FIFO status on the FPGA, elements to write tells you if there is room.

You could also try sending counter values to see if data is really being dropped or you have other issues.