Lowpass Filter Design question

[joedowdle]

Okay, so we had an NI rep here yesterday when I was out of the office for the afternoon and they came up with an alternative method.  It works good when you are reading from a DAQ card directly but since my data is going through the FPGA and then through a FIFO between VeriStand and my filter code it is running into issues.

The method uses the Filter and Arithmetic Mean Express VI's (I attached a screenshot of the block diagram).  It gives a very stable value but for I keep getting Error 20352 which is a contiguous data error.

I have 48 channels that I pass through a Convert to Dynamic Data with the setting "1S Array of Scalars - Multiple Channels."  Then it goes into the filter VI and then the mean VI.  On the output it goes though a Convert From Dynamic Data with the setting "1D Array of Scalars - Most Recent Value" (I also tried automatic).  With this data analysis the loop wityh the FIFO is about 50 Hz.  I set the Lower Cut-Off of the filter VI to be 0.015.  Yesterday they used a 6th order low pass filter.

I have gotten it to work - kind of - with one channel.  When it did work I still got the contiguous data error but I would get a "correct" reading.  This was attained by sending groups of samples of each channel to the filter instead of an array of singles values for each channel.  It would show close to the correct value (scale/offset were off) and was stable.  As soon as I expanded it to include all the channels I get this error.  Also it doesn't output the right value.  At "0" I get a reading of -128.1081.

Do you have any familiarity with why this might be happening?  Thanks.

[johnsold]

I cannot help much here. I do not have any FPGA or VeriStand experience.  I very rarely use Express VIs and I hate the Dynamic Data Type because you really have no control or knowledge of what is going on inside.

Wild guesses: In converting to and from DDT some information gets lost or is not converted in a compatible manner.  In going to DDT there is no timing information included (or even any way to include it!), so some sort of default timing is assigned. My guess is that the subsequent conversions have default timing which the Express VI interprets as non-contiguous.

Wild Guess 2: Same as above but this time it involves the way the multiple channels are combined.  The data is probably mixed up some way so that you get the large errors.

Lynn

[srm@viewpointusa.com]

why aren't you filtering on the FPGA before you send up to veristand?  why didn't the NI guy recommend you do this?  works very well without burdening the upper layer software.

with the 9205, you still have to be concerned with aliasing depending on the bandwidth of the noise from the current transducer.  if you can characterize the bandwidth, that will tell you the sampling rate and filter to apply.

[joedowdle]

I cannot answer why he didn't suggest that.  I am a relative new LabVIEW programmer and the FPGA code used is the first such code I've programmed.  Could you tell me what a good way to program filtering into the FPGA?  Thanks.