Max acquisition rate with USB-7855R

[dlathrop]

When I started this, I was expecting the FPGA I/O node to produce 16 bit integers (the ADCs are 16 bit after all), so I was a bit surprised that I was getting 27 bit fixed points. If there is a way to change this, I don't know it.  The FPGAs are target to host DMA's, and this card only supports three of them.  I was originally using only one, and going to two did speed up the loop by four ticks (as expected).

If I could get the 16-bit values, bit pack them into two U64s, and write them to two FIFOs, I could get the write to FIFO part of this down to 1 tick, and everything would run in 41 ticks, just one tick from my goal.

I'll work on sharing the project. The host VI is large and complicated. I'll probably just remove it and send the project without it with a short description of the FIFO read part of it.

Thanks

[dlathrop]

I solved the problem.  I connected the outputs of the FPGA I/O node to shift registers, then used the shift registers to write to the FIFO on the next iteration of the loop. So the FPGA I/O node and the write to the FIFOs can run in parallel.

Thanks everyone for you help.