Measuring FPGA Latency in a Regular While Loop — Tick Count Not Accurate

[AJAYY06]

Hi everyone,

I’m working on a LabVIEW FPGA project where I generate a digital HIGH–LOW signal inside a regular While Loop and want to measure the latency between when the output is generated and when it’s observed.

I tried using the Tick Count / Tick Rate VI on the FPGA to measure this latency, but the values I’m getting don’t make sense — they are inconsistent and don’t match what I see on the CRO.   

A few questions:

1. Why is Tick Count / Tick Rate unreliable for measuring latency on FPGA?

2. What is the best-practice method to measure FPGA latency deterministically in a While Loop?

3. Are there any tips for correlating FPGA-measured latency with what I observe on a CRO, given IO and probe delays?

Thanks in advance for any advice!

[Intaris · Accepted solution]

You're going to have to attach code or a picture or both.

[AJAYY06]

[Intaris]

Instead of toggling the boolean each iteration, why not just toggle it once and wait for the input to respond?

[ZYOng]

You are not using FPGA Tick Count VI in your block diagram.

If you want to count using shift register, you need to replace while loop with Single Cycle Timed Loop.

[AJAYY06]

iam using counter to find the how many tick does it take to read hing value,and also checking with the tick count vi but getting the diffrence of both value is zero ,before i was running these iam setting the value low at those pins..... the above code is okay wheather i change the code give me some ideas

[GerdW · Accepted solution]

Hi Ajay,

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@AJAYY06 wrote:

 the above code IMAGE of code is okay wheather i change the code give me some ideas

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We still cannot debug images with LabVIEW…

But you could cleanup the block diagram, so errors cannot hide so easily!

• You don't need to compare booleans with TRUE…
• STRAIGHT wires!
• Descriptive labels on ALL controls and indicators…
• …

[AJAYY06]

YOU CHECK WITH BELOW VI