Memory options in FPGA

[Roberto_CARTIF]

Hello,

I am working with a PXI-7811R FPGA to acquire signals from several encoders. The data is stored in memory blocks (generated with the Memory Extension Utility) that are used as buffers that are transferred to the host application when the blocks are full.
With this application I have used the 99% of the FPGA, and I want to know what is the best method to reserve memory for buffered acquisition in a FPGA when you need more than the 16K reserved in the FPGA memory.
I've looked inside the blocks generated with the Memory Extension Utility and I've seen that they are built using arrays. As in the FPGA User Manual is said that arrays mustn't have more than 32 elements, I don't know if using this memory blocks is a good idea (my memory blocks are larger than 32 elements).
I don't know if using FIFO or FPGA memory for some of the blocks will reduce the compilation time and the number of occupied slices in the FPGA.
Can anybody tell me how the memory allocation works in the FPGA? Are the 16K of FPGA memory always available although I have used more than 16K whith the Memory Extension Utility? Are independent both types of memory?

Thank you,

Roberto Arnanz
R&D Engineer
CARTIF
www.cartif.es

[jdigiova]

The code inside the express VI for the memory extension utility shows array usage, however the FPGA code that is actually generated from the memory extension utilities does not use arrays. The arrays are there for emulation behavior. You should not make any changes to the memory extension utility VIs (they are optimal as they exist).

You say you fill a block of memory and then send the data to the host. How large are the blocks of memory that you are filling and what type of indicator are you using to send the data to the host? For example are you using one large array, or do you repeatedly read elements out of memory? There are 80kB of memory available on the 7811R. If you use the memory VIs that ship with the product you will have 64kB (80kB-16kb=64kb)available for FIFOS, LUTs, or the memory extension VIs.

Your application sounds like a FIFO (using block ram) would be the best option for transferring data to the host. How many channels do you read? Suppose you read 4 channels. I would create an acquisition loop that reads the 4 channels and puts there data into a 4 element array. Than I would autoindex the array with a for loop putting each element into a FIFO write. I would also have a parallel loop reading data out of the FIFO. I would put the FIFO read in a for loop with 4 iterations. Again I would use autoindexing to build an array of 4 elements. On the host VI I would read the 4 element array. There are some examples for buffered data for FPGA. Here is a link for a example that uses the type of method described above. You will need to modify it for you device.

http://zone.ni.com/devzone/conceptd.nsf/webmain/8E999A74E43AC76186256F5E0068CFAC

Joseph D.
National Instruments

[Roberto_CARTIF]

Thank you for your answer Joseph
The data I acquire with the FPGA are the edges of five encoder signals (ticks). I use four buffers of 1024 elements for each encoder that I fill with I32 numbers (some of the buffers are smaller beacause the encoders are slower). This buffers are built whith the memory extension VIs. Each time a buffer is complete an IRQ is generated and the host reads the data of the memory element by element using a parallel loop as you mention. All the data is served to the host in the same loop that ask for a memory block and a memory position inside that block.
My problem is that I have the 99% of the FPGA slices used, and is impossible to introduce new code I need. When I use FIFOs instead of memory blocks the use increase over the 100%. The same occurs when I try to build any array.
But I think you have already answer my question. I think there is no way of optimising the use of the memory because I am using the memory extension VIs. So probably the only solution is to eliminate some parts of the project if I want to introduce more functions or reduce the number of buffers and see if the transfer ratio can be mantained without losing data.

Roberto Arnanz
CARTIF

[Jorge M.]

Hello Roberto,

have you checked this KB? It explains how to switch the way of compiling code for the FPGA, using either SPEED-efficient or AREA-efficient code.

http://digital.ni.com/public.nsf/websearch/EE940C191DDCE9CE86256E5500783A4D?OpenDocument

Regards,

Jorge M.