Missing data when streaming to and from FPGA via DMA FIFO

[tanmayj99]

Hi,

I am using a PXIe 6594 along with a PXIe 5841 to generate AM and FM signals. To do this I am sending the message data (eg. audio) via a DMA FIFO from the host to the FPGA. I've noticed frequent discontinuities in the output signal. 
To debug this, I created a stripped down version of the FPGA code where I am reading the Message FIFO on FPGA and sending it back to host via another FIFO. The data logged from the return FIFO also has discontinuities. I am also logging each time output valid from the FIFO read goes false on the FPGA, but it is always true. I have also tried varying the requested number of elements as well as the requested host-side depth, but to no avail.

A few things to note:

My FPGA SCTL is running at 160M, whereas my message signal may have varying sampling rates. To take care of this I am using a fractional counter on the FPGA where I read the next FIFO element after a certain number of cycles (e.g. if my message sampling rate is 40M I will read the FIFO only 1 out of 4 cycles. For the remaining 3 cycles I am holding the old value using a feedback node)

On the host side, I am continuously rotating the message array based on the number of empty elements remaining. From my testing, the issue does not seem to lie in this rotation.

I have been racking by brain for a while, but cannot find the source of the issue. Any help is appreciated. Hope I have clearly explained my problem.

I am attaching my FPGA and Host codes for reference.

TIA.

[Terry_ALE]

There's no lvproj and the FPGA VIs are password protected.

How are you handling handshaking and are you checking for overflows (or underflows)?

[Intaris]

As Terry says, you need to monitor the status of the DMA when writing from FPGA. If the data is not written properly, you need to wait for the DMA FIFO to have space to write the data. Incrementing through your data to send when the FIFO is not ready to receive new data leads to data loss.

If you are streaming, you need to make sure you are not sending more data than you can read per second. If you are not streaming, don't iterate to the next data point if the FIFO is not ready for data.