If I were trying to create an FPGA PWM signal, I think I'd write some "calling VIs" that live in the RT Target that houses the FPGA (say, a cRIO). One would be a VI that simply sets a Boolean Control on the FPGA Front Panel to True (Run) or False (Stop), . The other would be one where you set the PWM Frequency (in Hz, maximum, say, 500 kHz). Here you "do the math" to create two U16s representing the "High" and "Low" times for the PWM waveform and send these numbers to the FPGA. This keeps all of the math in the Host -- the FPGA just needs to deal with one Boolean and two U16.
So what does this look like? As with everything in the FPGA, you start with a "Do Forever" While Loop (wire "T" to the Stop indicator). You need a two-chamber Sequence Structure. The first Sequence Structure has a "Wait" with the High time wired to it, and the "Run" Boolean wired to the input of your chosen Digital Output line. The second Sequence Structure has another "Wait" with the Low time wired to it. And that's it!
I recommend initializing the three FPGA Controls, "Run", "High Time", and "Low Time" to "False", 500, and 500 (which configures a 1 kHz 50% Duty Cycle Pulse Train, but turned off, so nothing happens until you call "Run PWM" (on the Host) with Run set to True. [I presume you know how to do this]. Notice that the Pulse Generator in the FPGA runs continuously, looping every High Time + Low Time microseconds (which you can change whenever you want, but should probably turn the Pulse Train "Off" before changing). When it is turned On, the Digital Out goes High, then Low, but when turned Off, it goes Low, and then Low. Make sense?
Bob Schor
