Hi, I'm tring to implement a low-pass decimation filter on FPGA (9101) for all 32 AI channels of the 9205 (6 KHz/ch to 1 KHz/ch). I used the DFD stepbystep example vi to design my filter. Currently I'm transfering data channel by channel from the module to a Target-scoped FIFO. The filter reads from this FIFO, filter it and output to a DMA target to host FIFO so that the RT controller then reads them. The filter is not applied to the data channel-by-channel, it is rather applied to all the data in the FIFO. I don't think this is the right way.
The question I have is: What is the best way to do filtering one channel at a time? I can use 32 FIFO and send them thru the filter one at a time, but I'm not sure this is giving me the best performance, as I'm running the AI module at close to maximum sampling rate (aggregated 250ks/s). I need the most efficient way of doing this without running out of space on my FPGA. Any suggestions?
