Multiple FPGA loops to solve 8 channel AI / 4 Channel AO with PID compilation problem

[trouinky]

I think I mentioned in a previous post that my problem was associated with the 40 MHz clock - I'm only using about 40% of the gates, memory, etc. with my code, which now runs thank's to the added 30 MHz derived clock . . .

[Jennifer_R]

Hi Thomas,

It sounds like your code compiles with the modified PID VI until you add a FIFO, correct?  How many FIFOs are you using?  Could you post the current version of your code, or at least the main VI with the FIFO added? 

[trouinky]

Actually, the code compiles fine now, even with the FIFO.  What I've done is added a separate loop that uses local variables to send the measured values to the fifo - the top half of the 32-bit word is a "header" that indicates the measurement type and device, while the bottom half is the actual variable value (reconstituted on the host with the appropriate scaling values pulled off of each module).  The variables are written in order (the header is a number that increases inside a stacked frame, then FIFO output loop repeats; not the most elegant technique, I know), and the host checks the top half of each word to determine which device, which measurement, etc. . . . This is ideal for me because no matter when I pick up the FIFO stream (not always interested in looking at this data since all decision making is actually done on the FPGA side once the PID on switch has been thrown) the host knows which data is which.  And I never lose a single data point, although I plan to add some error correction if this does happen.  I could actually compress the measurements for each device down into one word, but I don't really need to at this point.


Message Edited by trouinky on 06-16-2008 04:56 PM

[Jennifer_R]

Hi Thomas,

I'm glad to hear that you have a working application now.  Thanks for sharing your solution!

[trouinky]

So now I need to kick up the throughput between the host and FPGA.  I have a measured value (AI) and a calculated value that I want to send back to the host (four channels/devices, for a total of 8 pieces of data).  What's the best way to multiplex this into the FIFO stream.  I've seen a couple of examples that are EXTREMELY complicated (many many channels).

I'm currently attempting to create a 32-bit element where the top half is a unique header and the bottom half is the actual value.  That would allow me to inspect each element on the host to determine what the data is, no matter when I start visualizing the data (all the work is done on the FPGA and doesn't necessarily have to be visualized at all).

Any advice would be greatly appreciated.

Thanks!

Tommy R.

[Jennifer_R]

Hi Thomas,

It looks like you are already using the Join Numbers function, which is useful to efficiently transfer data in 32-bit blocks.  Then, generally, it is a matter of writing the data to the FIFO and knowing the order when reading on the RT Host side.  If the data is stored in an array, you can use an auto-indexed for loop to write each element to the FIFO.  Otherwise, write the data in the same order each time or else you can check the header to determine the channel once the data is read.