Multiple NI 9402 Performance Limitiation Discovered

[csduffey]

Hello all,

I seem to be a magnet for timing related issues with the cRIO and FPGA,  I have a NI 9113 four slot backplane with two NI 9402 High Speed DIO cards and am using a 9022 RT controller, LabVIEW 2009, latest cRIO version.  When I selected the NI 9402 I read the spec sheets and it clearly states that a 9402 can run at 20 Mhz I/O for two channels and 16 MHz for four channels.  I had come up with a FPGA scheme where I was going to run the two boards in complementary cases of a 40 Mhz SCTL thus achieving a combined acquisition of 40 Mhz - this method DOES work exactly as I had hoped using a SINGLE channel on each board.  But here is where it gets weird,  I built a data generator to drive the input using one of the unused channels on the first card - this was also built in a SCTL and should run at a maximum rate of 20 MHz - but once compiled everything will only run at 16 MHz.  So the limitation for channels on a NI 9402 appear to be for ALL installed NI 9402 cards  - to verify  iinstalled a third 9402 and moved the generator to its own card - so that each card would only have ONE channel being used - guess what, 16 MHz is best rate...  I think this is probably a bug, I can see no technical reason why each board should not independantly be capable of running at 20 MHz if only two channels are used on it.  I suspect that there is some kind of rule in the Xilinx tools that counts instances of channel access on the 9402 and neglects to consider that it is on a different board.... Any thoughts LabVIEW FPGA gurus ????

Thank You

[srm@viewpointusa.com]

while I can't verify your use case exactly, I believe it based on some other observances with I/O that run on a similar vein.  even though there may or may not be a absolute reason for the limitation, the current implementation probably does not do what you want it to do.

[Verne_D]

Hi csduffey,

This not something I've seen before specifically. I'm going to poke around a bit more and get back to you. My suspicion is that this MIGHT be a backplane limited consideration, but the specifications certainly do not cover the distinction. I'll get back with you after I do a little more hunting.

[csduffey]

Thanks for looking at this Verne,  I was really counting on the thing meeting its specifications (which technically I guess it does if its the only NI 9402 in the stack) !  I can undertsand the limit on a per interface basis but I would think that if the backplane wasn't capable of running at 40 MHz per slot we would see problems with lots of other C modules - Looking forward to a solution !!

Thank You again !

[Verne_D]

csduffey,

Would you mind posting your FPGA vi? I want to see how you've built this thing.

[csduffey]

Here is an example that will exhibit the decreased sample rate - This a three NI 9402 setup with a single channel utilized on each C module (DIO 0)

[Verne_D]

Hi csduffey,

When I compile your code, it meets timing. Maybe I'm misunderstanding the question. Is the 16/20Mhz split you're talking about the maximum I/O switching frequency? How are you observing the failure to go faster than 16 MHz? Are you scoping your output?

[csduffey]

As you suggested,  I put a scope on the output of the generator and made a slight change to the code to allow me to vary the frequency of the output - I confgiured it to generate a 1 MHz square wave by measuring the output using the scope - on my system that equated to a period of 36 ticks (18 high and 18 low) inside the SCTL - right away this doesn't make any sense (with a 40 MHz clock it should be 40 ticks, 20 high and 20 low) but then proceeding to the input part of the design - with a 1 MHz sqaure wave coming in I should see 20 high samples followed by 20 low samples, instead I see 16 high and 16 low AND the ingested square wave has discontinuties due to the beating of the sample clock against the actual 1 MHz input - a scren shot is show below of the 1 MHz signal as seen by the dual NI 9402 cards

[csduffey]

So to be clear - I am running the data ingestion loop at the maximum rate of 20 MHz per channell with two channels interlieved to provide an effective 40 MHz sample rate - I am using this to digitally sample a data stream - the output side which I am currently using to generate a test signal will eventually be used to generate a 10 Mbps manchester endcoded output stream (20 MHz clock) so hopefully both input and outputs will be running at 20 Mhz - my observation after looking at the scope is that this is not affecting the maximum switching rate for the output - but the input is affected somehow

[csduffey]

Another clue - you cannot run two separate NI 9402 cards in separate/different clock domains.  Clearly this tells me that the tools are not looking at multiple 9402 cards as multiple cards,  the cards will run alternate clock domains but they must be the same...