Multiple NI 9402 Performance Limitiation Discovered

[Verne_D]

Hi csduffey,

I'm working on getting a system set up still.  I appreciate your patience, and I'll let you know as soon as I've got things running.

[Verne_D]

csduffey,

I've been able to replicate the same behavior you're seeing and I'm in the process of trying to derminine exactly why it's happening. I'll keep this thread updated.

[csduffey]

Verne,

Any progress or additional information to share on this ?

Chris D.

[charris]

Hello csduffey:

I talked to Verne today (He's been out of the office), and he's working with one of our R&D  engineers to isolate a cause. We'll let you know as soon as anything surfaces, and Verne will update you tomorrow in any case.

I apologize that I can't give you anything more concrete at the moment, but we are still working on the issue.

[Verne_D]

Hi Chris,

I aplogize for the amount of time this is taking, but you've run into a rather subtle issue that has proved difficult to troubleshoot. I've got some of the guys in R&D looking over things and I'll let you know what they find. I'll update this by midday tuesday with the state of things.

[Verne_D]

Hi Chris,

Here's an update of what we've uncovered on this issue.

The Maximum I/O Switching Frequency is a property of the hardware that denote the fastest rate the interal circuitry can respond to a change in state. This does have anything to do with how fast the I/O node executes. The choke point we're seeing resides in the communication between the FPGA and the real time host VI.

Try this: Store the data you're measuring in shift registers and send an array of these points on the nth execution through the DMA fifo. The code should looks something like this on the FPGA:

This will allow you to store the data on the FPGA and send it less frequently to the RT.

Let me know if this helps. Also, monitor errors on the DMA FIFO. You can add error terminals on the FPGA VI to give this a shot. Let me know what you find.

[csduffey]

wow - so what is the bottle neck, actually setting up the DMA transfer ?  So what do you think about setting up a counter that goes to say 32 and then mutliplying the bit value out of the I/O node by the counter value and adding to a single U32 shift register ?  I can't imaging a multiply and add would take terrbily long on the FPGA, and then transfer the U32 to the DAM FIFO, so it would transfer a word every 32 bits.  But at any rate I'll give it a shot !

Thank You !

Chris

[csduffey]

BTW - the fact that you cannot run two NI 9402's in different clock domains is clearly a different problem than this - should I officaily submit a service request on this ?

[Verne_D]

Hi Chris,

I don't think the operations are what's slowing down the transfer. More likely its the way the DMA FIFO is being written to. I'm not sure I understand exactly the multiplying scheme you're descirbing here, but amassing points and sending less frequently is what I'm suggesting. Maybe post some code detailing your algorithm.

Regarding the timing domains, I agree, starting a new one's probably a good idea.