NI PCI-783xR Digital I/O Resolution ?? bits

[Massif]

  Dear,

I would like more information about the Multifunction Intelligent DAQ using LabVIEW FPGA.

What is the resolution of the Digital I/O on the NI PCI-783xR (PCI card)?
I have see 16 bit for the analog input but nothing on the digital input.

Regards

  Julien 

[TCPlomp]

I think you are looking for the port-width of this device?
An digital line has a bit resolution of 1.
The port-width (number of lines per port) varies from device to device.

Ton

[Massif]

   Dear TonP,

And thank you for yor response.

No, I'm looking for the data size per line.

Example:

In this data sheet for the analog input

Analog Input
Number of Channels	4 SE/4 DI
Sample Rate	200 kS/s/ch
Resolution	16 bits

There is nothing write for the resolution of the digital I/O.

Is it 16 bit? I need I32 bit for the digital input.

  Massif

[StevenA]

Massif,

Can you elaborate on why you need "32 bits of resolution"? This board has 56 digital IO lines.  These lines can be programmed in the FPGA to acquire at rates of up to 40MHz. As Ton said, you only have 1 bit of resolution per line, that is, there is not programmable voltage levels on these lines.  They will register either ON or OFF according to the Digital Logic Levels  (http://www.ni.com/pdf/products/us/2005-5528-301-101-D.pdf) specifications.  This board does not support changing the logic voltage levels on the digital IO lines.

Steve

[Massif]

 Dear,

I have to explain my application a little bit more. On the FPGA target I have created 2 counters of an event depending of 8 digitals signal.  But this event can arrive more than 2^16 during one application.
How I can transfer thess numbers with the R series cards?

"store your compiled LabVIEW FPGA application in the onboard flash memory of any R Series device"
"You can configure the digital I/O lines as custom counter/timers" -> I think at started we can create internal counter and transfer the result at 40 MHz.

Can I used 32 line to transfer the number?

I can't transfer all signal to the host, because my application sould draw a graph in "real time". That why I have created a batch rate with internal counter of event inside the FPGA.

I hope I am enough clear.

Regards

  Julien

[K_Bull]

Hi,

On the product page, on the specifications tab, you can see that the Counter/Timer Resolution is 64 Bit.

Regards,

[Massif]

  Dear,

I'm very sorry but i think there is something I don't understand.

There are
56 counter/timers -> 64 bit
56 channels DIO -> 1 bit

So how I tranfert the counter timer? I have (2 counters on my application)
I have to used the DMA channel? (because the DIO channel is just 1bit)

Regards

   Massif

[UliB]

Dear Massif,

1 digital Line (1 bit) is represented as 1 boolean Value in FPGA. If you need a Counter with 32bit resolution just configure a control / indicator / constant as I32 or U32.

Look at the attached picture (no real FPGA-Code). Every change in the digital line from 0 to 1 increments the counter. The counter itself has an resolution of 32bit, because the constant is I32.

One simple method to transfer the value of the counter to your host is to read the control from your host-VI. Another method is to use DMA FIFO between FPGA-VI and Host-VI.

Hope this helps.

Uli

[Massif]

  Dear everyone,

All is clear now, thank you to all people who helped.

   Massif