I just found something out which surprised me a little:
I am using a target-scoped FIFO on FPGA (Virtex 5) to send commands to a parallel loop which parses those commands and sets up some parameters. I designed the data in such a way that the highest 8 bits are a command value. This gets parsed to an enum for parsing with the default value (zero) set to no-op so that default data won't alter any parameters. OK, good I thought, that's that problem solved.
Erm no. Problem is that a FIFO apparently repeats the last sent value if no new values were sent in the meantime. I'm using the FIFOs in a timed loop, so maybe behaviour is different without timed loops. I had a "Trigger reset" command for an oscilloscope which was getting triggered may more often than it should. Problem was that the last command was being repeated infinitely as the FIFO keeps outputting the last value upon timeout until it received any new data.
So, take case to wire up the "Timed out" output and only parse the parameters when the time out is false even if you think you've set up your messaging in a fail-safe way.
