Well, not knowing you had a solution up and running would be part of my reasoning....
Still, the SCTL part is a steep learning curve.
On your included image, the timing of reading from the FIFO does not neccessarily represent the same timing as you write to it (it might, it just depends on your hardware). For me, just to be pedantic, I would include the timing of the acquisition in the FIFO to the second loop so that you retain the actual acquisition timing for proper results.
Also, didn't you write earlier that you wanted to react within microseconds? With a loop timer of 200us, that's not what I would have understood from your text. Trying to solve the problems as you describe them.
I'm pretty sure I could write code 10x faster (useless if your analog hardware doesn't support it) and with 10x less resources (useless if you don't need anything else on the FPGA) and at least equivalent accuracy, but as long as you have something up and running, then you're doing fine.
