My labview code has 14 timed loop to control 14 channels which are used to cycle (charge then discharge) batteries.
The problem is any channel could have a random lock-up. When that happened, the batteries attached to that channel got drained completely and that damaged the batteries and some hardware. During the course of debugging, I found that adding some file I/O's to the code can make this problem happen every time, and I think an unknown error happened at the analog read vi (no error popped up) that causes the timed loop to hang. The RT controller also communicates to the host PC. From time to time, it is possible that the busy traffic causes the system to retry sending messages.
So, my theory is the occasional high ethernet traffic causes some unknown error to the analog read and that crashes the timed loop.
1. Is my theory possible?
2. When the code in a timed loop crashes, is it true that the the main program and other timed loop can still run?
3. I understand that only one watchdog is available in the RT system. Is there any workaround so I can put one watchdog to each timed loop? A standalone watchdog loop could not catch this problem because the main program was still running.
Thanks much for your help.
My system config: PXI-1031, PXI-8184, PXI-6221, LV 8.2, LV RT 8.2.