Options to transfer data from host processor to FPGA

[StMartin81]

Here is an example of a SubVI I'm working on. The top loop stores the sequence into a FIFO. The second loop will execute the sequence and in the third loop I set the pins of the slow output modules. This code needs to be placed in a multi cycle loop.

What I could do is to make an indicator for the pin states and then set the pins states in my toplevel FPGA VI. But when I would remove the single cycle timed loops how would I initialize my FIFO? I guess I would have to initialize it in my toplevel FPGA VI and then pass the signal as a control to the VI? Or is there a better way to achieve this? In the toplevel VI I would then use a sequence structure to first initialize my signals and in the second frame I would start my loops. But what would be the benefit of using a sequence structure? When you look at the attached block diagram you can see that I initialize a FIFO before the signal enters the while loops which, as far as I understand it, should basically do the same as the sequence structure.

[LocalDSP]

I agree with all your statements. The idea here is to use a Target-Scoped instead of a VI-Scoped FIFO and to initialize it at the top level before entering your main SCTL (so basically moving the concept you are using in your subVI to the top level. As you mention, you'll have to pass the FIFO reference as a control to your subVI.

The suggested sequence was only necessary if your initialization process didn't have any direct relation to your main code (for example if it had been an FPGA VI Start method), so flow diagram controlled sequencing if fine in your case.

Hopefully by passing all your parameters with control-indicators you'll be able to get rid of your globals (maybe using a few local variables to transfer data between your SCTL and While loop.

In your subVI you have two SCTLs running at the same (Default) rate. Again, you can put all your SCTL code inside the same loop unless you see a cosmetic reason for not doing that. One or two loops will behave 100% the same.

[StMartin81]

Unfortunately I can't pass a FIFO reference to my SubVI because this seems only to be allowed when the SubVI is reentrant which I don't want it to be. If the FIFO is initalized empty when the FPGA starts running then I can live with that, but I wonder if it is possible to initialize the FIFO if needed.

[LocalDSP]

What don't you want your subVI to be re-entrant? Your original subVI had both loops and un-initialized shift register, so running multiple instances of that subVI would not work if not re-entrant (one instance would run continuously so the other one would never run), and if you plan to only have one instance of that subVI making it re-entrant won't affect behavior.

On a different note, you may know that already but when you move your subVI loop at the top level you don't necessarily need to move the shift register to the top level as well. You can use local shift registers as shown on this concept diagram.

[StMartin81]

Yes, you are right! Of course I want my SubVIs to be reentrant! 🙂 I got confused here.

I used local shift registers to initialize my signals but I was not sure if that really works. So thanks for reaffirming me that this is the correct way to do this! 🙂