PID (FPGA) Gain Values

[Stirl]

Hi folks,

i´m using a PID-Module on the FPGA level.
Now i want to get the system stabil. Usually the I-gain is a very small value (i.g. 0.005). But you get 1,2,3,...
With the P-Gain is everything ok. It´s working.
If i increase the I-Gain, the system is freaking out. So, i need smaller values.
And the D-Gain has no influence of the system at all.
Well, i know that the the FPGA system doesn´t accept fluent point values.
From my point of view i must change something in the default option.
But i dont know exactly what and which values i have to change.

Do anybody have an idea what to do?
Thanks a lot
  Andi

[StevenA]

What version of LV are you using?  And, what PID function are you using?

[Stirl]

Hi,

i´m using LabView 8.5.0.
It´s the normal PID-Module which you can choose on the FPGA Level.
The layout of the PID is attached.

Cheers
   Andi

[Michelle_N]

Can you please post the name of the VI that you are using?

Thanks!

[StevenA]

OK, this is the built in FPGA PID vi (new to LV 8.5).  Take a look at the help screens.  Double click on the PID express vi and read how the PID gains are implemented.

This is the text right out of the help.

PID (FPGA) Details

The Express VI represents the PID proportional, integral, and derivative gains as 16-bit integers, where the upper 8 bits represent the integer part and the lower 8 bits represent the fractional part. Given the Proportional gain (Kc), Integral time (Ti, min), and Derivative time (Td, min), respectively, the Express VI scales these gains according to the following formulas.

[Michelle_N]

To add to this here are some general PID KnowledgeBases: PID Theory Explained and PID Control
 
Hope this helps!

[danreb]

I have the same problem as you. In my case I think that the trouble is the sampling time (25ns) that is so small that almost any valour of the Ki constant make the system trip, and also because of that the derivative time is useless (also you can check to use 1/Ti, there are different ways of considering the PID constants).
I started using other PID VI, I get it on a sample from NI (CRIO motor control, altough you don´t have a CRIO you can use that PID VI, it´s more complete). Maybe you have the same problems at the beggining with it, but you can change the values of the constant Ilim (this is the antiwindup value for the Ki constant) and things get much more better just with Ki=1. Things worked that way but I don´t really liked it.
I finally decided to use my own PID algorithm, I´m still working on it, and by now I have the same troubles, but in the future I will scale the Ki, Kc and Td inside the FPGA module and decrease the PID sampling frecuency and hope everything starts to work fine at last.
Best regards.

[Stirl]

Thanks for all the help.

I tried a lot to get the system in a stabil run. I changed The normal PID with the Fixed Point PID. But this creates me a lot of noise.
Well, now i went back to the normal PID module by only changing the Kc gain.
I eliminate the offset by adding a value to the signal output.
This works pretty good for my application.
Cheers
  Andi

[danreb]

Good morning again.
I don´t think it´s a good idea to do that (just adding the offset). I don´t think that it works in every point. Maybe if you have a constant countertorque (in case of motor control) or similar works, but I dont think it´s the best way to do it.
You can try to decrement the frecuency of the PID calculations in order to avoid too much integrator effect or try to use an antiwindup limiter (I don´t know if you can use that PID VI has this option).
I´m developing my own PID for that reason, the FPGA work rate is two much fast and it make the integrative component grown very fast and the system doesn´t works very well. By now I´m having good results with it.
Best regards.

[Michelle_N]

Stirl,

To get rid of the steady state error (I assume this is what you mean by offset), you should try increasing the Integral Gain (in other words decrease Integral Time).

Does this makes sense?