07-26-2008 11:02 PM
07-27-2008 06:21 PM
07-28-2008
01:55 AM
- last edited on
10-28-2025
04:07 PM
by
Content Cleaner
Good morning,
I think your main problem is that the sampling time is too high. Don´t know if the Ts on the PID vi is the real or an stimated sampling time in order to do a rescaling. Now I´m working with a PID to control a system drived by a DC motor and I had problems with the Ki gain. I don´t know if you have access to the integral part of the PID with that VI, but if you have it you can use an antiwind up strategy in order to reduce as much as possible the overshoot ot the system.
Also, if it´s possible, try to use smaller sampling time (at least in the PID loop) to avoid the overshoot due to the integral part.
Finally, you can check this sample http://zone.ni.com/devzone/cda/tut/p/id/6143 . Maybe you aren´t using a CRIO, but you can use the PID VI in the FPGA VI, because it´s more complete than the one you are using, and it has an PID input (Ilim) to limit the integral effect so you could have better control of the system.
Best regards.
07-28-2008 02:58 AM
07-28-2008 06:50 PM
07-29-2008 02:07 AM
08-07-2008 10:51 PM