PID control in FPGA

[Barp]

Implementing your own PID is acceptable, but keep in mind that most of the 'additional' features of a PID as "anti-windup" and "bumpless transfer" are not part of it and, when dealing with a real system, you will need to implement those features too. The PID FPGA, which mimics the floating point version on host, has those features. Please look at the documentation:

http://zone.ni.com/reference/en-XX/help/370401J-01/lvpidmain/pid_overview/

http://zone.ni.com/reference/en-XX/help/370401J-01/lvpidmain/pid_vi_algs/

http://zone.ni.com/reference/en-XX/help/370401J-01/lvpidmain/pid_topo/

Now, on your question: yes, the loop time is the sampling time of your controller. Notice that, as you increase the sampling time, the range of your integral action gets reduced due to the limitation of fixed-point on FPGA. The PID FPGA uses Kp, Ki and Kd (on the terminal), but allow you to enter the Kp, Ti and Td (using configuration). If you want to do this process programmatically, you can use this VI to do the conversion and quantization from floating to fixed-point:

C:\Program Files (x86)\National Instruments\LabVIEW 2013\vi.lib\addons\control\pid\fpga.llb\PID FPGA Coefficients.vi

See also the shipping examples that is indicated in here:

http://zone.ni.com/reference/en-XX/help/370401J-01/lvpidmain/pid_on_fpga/

hopefully this helps...

[nmadhaneie]

@ravensfan: i need to practically implement this. so far i tried with the proportional part alone. but i m not getting the expected conrol. Through simulation using Matlab i ve got some good results with pid so only i am trying to work with that.