PXI-6682 read IEEE-1588 timestamp from 7953R over RTSI bus

[John80]

Hi,

I am relatively new to LabVIEW programming, although I have two years of hard experience using LabVIEW FPGA tools.

So, I have a PXI-1033 chassis, and I have plugged in an PXI-6682 IEEE-1588 card into slot 2 and a PXI-7953R card into slot 4.  (Random selection for slot 4)  What I am trying to do is read the GPS timestamp from the 6682 card via the RTSI lines directly into the 7953R FPGA card.  Unfortunately, I have no idea where to start and what to read, and all the examples (keywords: RTSI, IEEE-1588)  that I find are for how to read the IEEE-1588 timestamp inside the Host Operating system and nothing tells me how to do it directly from the FPGA.  My goal is to build a machine that timestamps network packets that are being read by the FPGA hosted inside the PXI-7953R card.

Can anybody point me in the right direction?  I basically want to learn more about RTSI, where the PXI-6682 outputs its IEEE-1588 timestamp, and how data is transferred over the RTSI bus from inside a PXI chassis.

Thanks,

John

[AlejandroZ]

Hi.

The 1588 Ethernet packet timestamps are not readable.  Only the driver can read those timestamps, as it uses them to steer the timekeeper clock.

You can read IO timestamps in LabVIEW and LabVIEW RT with the 'niSync Read Trigger Time Stamp' VI.  There is no built-in way to export it via RTSI.

However, I am not quite clear about your application.  Where is your Ethernet traffic going, to the PXI-6682 or to the 7953R?  If it is going to the 7953R card then you can make that card generate an event on RTSI when you detect an incoming Ethernet packet you are interested in, and have the PXI-6682 timestamp that RTSI line.  Then you can read the timestamp with the 'niSync Read Trigger Time Stamp' VI.

Hope this helps.

AlejandroZ

[John80]

Thanks for the response Alejandro,

I have a 7953R FlexRIO board with the Mimas Prevas Dual Gigabit Adapter Module (http://www.prevas.com/ethernet_simulator.html) plugged in.  Ethernet packets enter the Mimas Dual Gigabit Adapter and then go directly to the FPGA as raw Ethernet frames.

From what you are telling me it seems like I cannot have a timestamp go from the PXI-6682 to the 7953R via the RTSI lines and to then be appended to the end of the ethernet frame before being retrasmitted out the other port of the Dual Gigabit Adapter. (With proper recalculation of the 32 bit CRC being done inside the FPGA of course)

I will do some more reading of the manuals and will then call NI Support.

Thanks again!

[viScience]

First off, what kind of accuracy do you need?  You could probably achieve 100us accuracy just by have tight RT code publishing the 1588 timestamp directly into FPGA front panel controls.

You might be able to do better than that if you take advantage of NI-SYNC driver capability to generate a clock signal to the PXI backplane.  Ideally, this clock would trigger from a PPS (pulse per second) locked to GPS.  Also you would still need to publish the 1588 timestamp to the FPGA but at a much slower rate since the clock signals would give you your finer resolution.

[Flamboyant]

Hi John,

I have NI PXIe 7966R FlexRIO and Prevas Gigabit Ethernet Adapter. I need to do ethernet analysis using these two. I know LabVIEW, but dont know how to access ethernet data from the Prevas.Is there any API or FPGA IPs available to do it. Or some example LabVIEW programs that will help me get started.

Flamboyant