Parsing Boolean Array in FPGA

[grkr]

Hi All,

Although I have programmed in LabVIEW many times, I am quite a novice when it comes to programming on an FPGA, and I have been learning as I go (which up to this point has worked with little issue).  However, I have been unable to resolve my latest issue, and the more I read about the FPGA, the less certain I am that what I am trying to do in even possible.

The task at hand involves reading in a set number of bits from the digital input/output lines of the FPGA and parsing these bits into specific words/"bytes."  For the purposes of the VI that I have attached, I have faked reading in a set number of bits by supplying three 26-bit words (78 bits total) that have been been defined on the front panel.  After supplying the specified bits, I am trying to parse the bit array into specific words that are given by the following logic:

1.  Search for a start bit of 0 (false bit).

2.  Once the start bit of 0 (false bit) is found the word that is trying to be parsed is the next 10 bits.

3.  After the start bit and ten data bits is a stop bit of 1 (true bit).

4.  Repeat steps 1-3, five additional times.

From the above logic, there should be six parsed words in total for the supplied VI.  Unfortunately, I cannot simply take 12 bits (1 start bit, 10 data bits, and 1 stop bit) at a time, as the number of filler bits in between successive words is variable.  The VI that I have supplied is one version of how I have proposed to accomplish the aforementioned logic, but I cannot compile the VI/project, as I continually receive errors that "Arrays must be fixed in size."  To my knowledge, all the arrays in the VI have been preallocated and the logic seems deterministic.

If anyone has any suggestion as to why this VI is not compiling, I would be greatly appreciative.  Thank you in advance for taking the time to look at this, and I look forward to resolving this issue.

With gratitude,

Gregory

[nathand · Accepted solution]

Unfortunately, you're going to have to rework this VI to make it run on an FPGA.  You can't relocate arrays in memory in an FPGA the way you can on a PC.  You have a variable-sized array as the output of delete from array, because the length input isn't fixed at compile time.  Also, two dimensional arrays aren't allowed.  Remember that when you code for an FPGA you're actually writing the hardware - each value in an array is essentially a circuit (this is my overly-simplified understanding).  The compiler can't allocate the right number of wires to carry an array if it can't determine the array size.  The array isn't in memory so there's no way to rearrange it at run-time.

There are a couple of ways you could work around this, all of which will require iterating through every element in the input array.  You could use an FPGA FIFO, and only put the values into the FIFO that are data (ie, loop until you hit a start bit, put the next 10 values into the FIFO).  Then on the other side of the FIFO, possibly in a separate loop, read 10 bits at a time to get your data words.  Another approach is to rearrange the array as you go.  Keep track of the current location in the input array.  Whenever you hit a start bit, move the next 10 bits (you may have to do this one at a time) to the current location in the input array, incrementing the current location each time.  When you've finished all the input, all the data words will be at the beginning of the array in 10-bit units, which you can then split out as needed.

[grkr]

Thanks for the suggestion.  After a few iterations of trial and error, I found a solution that incorporates your suggestion of moving one bit at a time.  I appreciate the help, as I am not sure that I would have tried moving one bit at a time otherwise.  As you cautioned, I was not able to sort multiple bits at a time, as LabVIEW maintained the error warnings that all arrays must be fixed in size.  Thanks for all of your help; I really appreciate it.