The outer loop executes FP Read and the case structure only once per loop iteration. In your case structure, you have a loop in which you're writing data to a file. The case will not complete until the inner loop is done. The outer loop will not continue until the case is complete. So your inner loop writing data to file always has the same data because the data is from only one call to FP Read.
You need to restructure your VI. You can remove the inner while loop structure, leaving the write functions in the case. Now you need to change the test for your case. The logic you had to stop the inner loop must be incorporated into the test for the case. I would add a shift register for bit 3 and one for Start time (the time at which you want to start saving da
ta). Update Start time any time bit 3 changes from False to True. Save the data if current time is less than 40 seconds greater than Start time. By the way, your note said 26 seconds but your VI said 40.
If you want to test if a particular bit is True of False, why not look directly at the original boolean array rather than converting the array to a string, then taking a string subset and then calling Match True/False String? When you say you're looking at bit 3, remember in an array indexes start at 0 (so the third least significant bit is index 2).
Look at the modified VI attached. I don't have field point so I couldn't test it. I would also wire the Error Out from the FP Read in the case in a chain with Error Out from FP Read (reading boolean array). Since I don't have Field Point, I couldn't wire it for you. You could wire all the Error Outs in a chain and delete the Merge Errors VI. Having separate Error Out chains for FP Reads vs. file I/O alows you to continue reading
data if there's a file I/O problem, but is that something you want to do?
