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Pattern Generation USB 6341

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Hi Vikrant,

 


@Vikrant_dhruva wrote:

I didn't understand where I can reduce my code,


See this:

As already shown in message #17!

(There are several other improvements shown in the image in that message!)

 


@Vikrant_dhruva wrote:

I edited the VI by including a digital trigger for synchronizing both as I am using an external clock on PFI02, I just used it on both.


In the last VI the trigger source constant is empty, this way the trigger will not work…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Message 21 of 30
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I have actually connected the trigger source, it was just not shown in the VI. 
Oh, I now see the improvement but what is the block that is connected after Equal?, I didnt get that one

And my original question still stands for analyzing the data I want to implement that without the use of shift register in the while loop as I think it might introduce some delay.

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Message 22 of 30
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Hi Vikrant,

 


@Vikrant_dhruva wrote:

Oh, I now see the improvement but what is the block that is connected after Equal?, I didnt get that one


It's the same function as you used after the FOR loop…

 


@Vikrant_dhruva wrote:

And my original question still stands for analyzing the data I want to implement that without the use of shift register in the while loop as I think it might introduce some delay.


Which shift register are you talking about?

(As also shown in message #17 there are simplifications possible on the data analysis loops…)

 

Why do you think a shift register will "introduce a delay"???

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Message 23 of 30
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Hi GerdW,
I was talking about the BER_new_Test.vi, on how to acquire real-time data. As, at a time I am only getting the 'x' samples only. Please refer to message #18

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Message 24 of 30
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Hi Vikrant,

 


@Vikrant_dhruva wrote:

I was talking about the BER_new_Test.vi, on how to acquire real-time data. 


And I still don't know which shift register you are talking about…

 


@Vikrant_dhruva wrote:

at a time I am only getting the 'x' samples only.


The DI loop runs as long as there is no error and no "Stop System" flag…

As there is no wait inside the loop it will run as fast as possible and show the "available samples" on your graph. (As programmed by you.)

 


@Vikrant_dhruva wrote:

I was talking about the BER_new_Test.vi, 

 

Please refer to message #18


The BER_new_Test is attached to message #20, while message #18 has the Digital-ContinuousInput VI!

(Also no shift register that corresponds to your question…)

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Message 25 of 30
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Hi GerdW, I meant to say that I wanted to do the things mentioned in message18, meaning
1. I wanted to get all the data for 'x' secs , lets say I run for 5 sec so I should get appended data worth 5sec, currently it just overwrites in each iteration (each sec) of the DI loop.

I want to do some analysis in real-time so need this whole data everytime, so I have to do by adding a shift register for the collected data, the method I know.

Thank you very much for your time and consideration. 

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Message 26 of 30
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Hi Vikrant,

 


@Vikrant_dhruva wrote:

Hi GerdW, I meant to say that I wanted to do the things mentioned in message18, meaning
1. I wanted to get all the data for 'x' secs , lets say I run for 5 sec so I should get appended data worth 5sec, currently it just overwrites in each iteration (each sec) of the DI loop.

I want to do some analysis in real-time so need this whole data everytime, so I have to do by adding a shift register for the collected data, the method I know.


In this case you need to collect all data:

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Message 27 of 30
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Hi GerdW,
I tried that but it is showing the result like below, somehow it has seperated the bits even though i have config it for only 2 channels.
And why was the sampling rate divided by 10 and anyway I am using an external clock source so shouldn't the sampling rate deciede the samples that will be acquired? I mean if f= 10kHz, meaning 10kbit/sec. So, for 5sec it should be 50k samples overall. If I understood wrong please correct me.

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Message 28 of 30
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Hi Vikrant,

 


@Vikrant_dhruva wrote:

I mean if f= 10kHz, meaning 10kbit/sec. So, for 5sec it should be 50k samples overall.


Why do you need a loop for DI task at all? You should just read 50k samples with DAQmxRead…

 


@Vikrant_dhruva wrote:

And why was the sampling rate divided by 10 and anyway I am using an external clock source so shouldn't the sampling rate deciede the samples that will be acquired?


Because it is "common sense" to read about 1/10 of the sample rate per iteration, resulting in a loop iterating 10 times per seconds…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Message 29 of 30
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Hi GerdW,

If I remove the loop then the data collected cannot be stored, because, if I run DI without the loop at f=10kHz, then it will only display lets say 10ksamples at a time even if I run it for lets say 5secs as it overwrites the previous values. And if I use the earlier method mentioned in message27 it is not appending the values.
Then, what method do you suggest for the current method for DigitalRead, if this seems not adequate.
(I will be running system in 1Mhz till 10MHz as well)

My goal is to basically compare the data in the 2input channels continously as long as I run the VI (real-time). I tried the comprison but data collection seems to be the problem.

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Message 30 of 30
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