Porting Virtex 5 CLIP to Kintex 7

[Intaris]

We currently use a Virtex 5 FPGA target (PXIe 7965R) and wanted to investigate the benefits of moving to a newer RT controller with a Kintex 7 FPGA target.

We use a third-party CLIP decigned for the Virtex 5.  I tried importing it into LV 2015 with a PXIe 7972R target (Kintex 7) but it complains about missing signals.

How much work is it to port an existing Virtex 5 CLIP to Kintex 7 so that we can do some compilation tests (compile time, device utilisation etc.)?

[Kyle_G]

In general, the more FPGA-specific primitives that the CLIP instantiates, the harder it is to port. If the CLIP is mostly standard RTL type logic, it can be ported fairly easily. If it relies on more specific device primitives, such as I/ODELAYs, I/OSERDES, PLLs, etc., this can take more time due to changes in these components between Virtex-5 and Kintex-7. For example, Virtex-5 IDELAYs have 64 delay taps spanning 5ns, while the Kintex-7 equivalent only has 32 delay taps spanning 2.5ns. Any algorithms relying on the wider delay span will need to be updated. The complexity of the design would also mean more or less work would need to be done to port constraints, and possibly additional constraints would need to be added.

That's assuming you're using a user defined CLIP. If you're using a socketed CLIP for an adapter module you'll have to purchase the FlexRIO MDK. This describes the changes to the socket and pinout that are required for adapter module CLIPs.

Kyle

[Intaris]

Yes, we're using a socketed CLIP.

I'll get in tough with our VHDL guys in that case.