Preventing case structure from changing once changed

[teebee2019]

Hi Community,

I'm using a cDAQ to monitor three sensors(0-10v). The VI has been made to detect when the voltage goes beyond a predefined threshold. Once the voltage exceeds the maximum threshold the case structure flips and stores the Waveform Chart for each sensors.

The problem is the voltage can go up and down after the first fault has been detected and this will mean the case structures will keep on flipping to TRUE and FALSE which results in a loss in waveform chart data.

I need some guidance on how to capture the waveform chart on the first and only time the voltage exceeds the maximum threshold.

Thanks in advance

[cbutcher · Accepted solution]

I don't have LV18 installed so I can't open your VI and check the non-visible cases, but it sounds like what you need is a latching boolean? By this, I mean not the mechanical action, but rather a trigger connected to a shift register or feedback node via an Or comparison, so that once true, it remains true even if the trigger becomes false.

This shows two possible implementations.

[RavensFan]

Store the boolean value in a shift register.  Initialize it with a false and wire it through the false case structure.  In the true case structure, feed a true out to the shift register.  The wire will be false until it turns true, then it will remain true.

Any even simpler implementation is to just OR the shift register with the result of the comparison.

[altenbach]

To keep a boolean TRUE after the first TRUE encounter, I typically use something as follows. (but with a little more code to allow resetting it, of course ;)):

Now, lets clear up some glaring race conditions and inefficient coding practices:

1. None of you value property nodes are needed.
   1. For boolean 1..3, place the terminals outside the case structure. Delete the value properties.
   2. You have the elapsed time in the wire above, so wire from there to the three case structures. Currently, the value properties are most likely read before (or maybe after! Nobody knows!) the terminal is written, giving you unpredictable results. Delete the property nodes!
   3. Same problem for the "start time". Use the wire and eliminate the property nodes!
2. "Array to cluster to unbundle" is pure Rube Goldberg. Resize "index array" for six outputs to get the same. No need to wire the indices. Also note that your "array to cluster" has the wrong output size configured (9 instead of 6). You can take the absolute value once on the array (or cluster), no need for all these instances. You could even use "decimate array" with two outputs and do all at once. Your "2" diagram constant should be orange, but you could also use "scale by powers of two" instead.
3. Building arrays by prepending elements is significantly more expensive for the memory manager. Why can't you append at the end? If you do, you can eliminate all the "reverse array" operations too!
4. Maybe it would be sufficient with a 2D array in a single shift register instead of having all that duplicate code..

(You did not include the subVIs, so I cannot comment more but I suspect there are more problems. ;))

Here's an example of my point #2: