Hi everyone, I'm using the HDL Node in LabVIEW 8.6 to try to import a VHDL design created using the HDL Coder of Matlab Simulink. The problem that I am having is that the design includes a state machine that the HDL Coder has created as a separate VHDL file that the top level VHDL should reference. At present, I have found no way to make the HDL Node correctly do this referencing.
I've attached the VHDL files, both "as generated" by the HDL Coder and a version that I've modified to make compatible with the HDL Node (as in changing clk_enable to enable_in). The QEI.vhd is the top level which references the state-machine in FSM.vhd. If anyone could suggest a way of incorporating these into the HDL Node then it would really help my (very) limited VHDL.
Thanks,
Andy
p.s. One idea that I think would work but that I'm not able to do (through lack of knowledge of VHDL) would be to take the contents of FSM.vhd and include it within QEI.vhd. If anyone could suggest a way to do this then I'm fairly sure that would also solve the problem.
