Problem with Self Implementation of SPI Master Slave

[westgate]

Hello,

i am trying to sent some small commands between two FPGA Cards via the PXI Trigger Bus.

I modified an Example of an SPI Bus Implementation.

My testprogramm looks like this:

If i compile the vi and run it in interactive mode the Master Data In Control is not updating when i click the first time on write. It updates only when i click a second time. Can somebody tell me why i see such a behavior?

With kind regards

westgate

[g_Ricky]

The only thing that I can see from your image is that you have not syncronized the loops. It's better to be sure both loops start at the same time but I'm not sure this will solve your problem.

[westgate]

Hello Ricky,

in the end both loops will run on different FPGA Targets. So it has to work without synchronising the loops on FPGA.

I think the synchronisation will be done by the slave loop because it waits for Rising and Falling Edges of CS Chip Select and SCLK SPI Clock.

westgate

[g_Ricky]

Sorry I have thought Producer and Consumer were running on the same FPGA. It's seem very strange.

Which mechanical action have you selceted for your button?

[westgate]

I have selected the switch operation. The reset of the button is happening at the end of the Flat Sequence of the Master Loop.

The strange thing is that the Slave Data In Control is updated imediately. So the code on the slave that is sending the Data to the Master has also been executed.

Fell free to test the Code the image is a snippet you can simply drag it into a empty VI.