Problem with compilation report

[Bluesky96]

Hi, I'm working on project involves implementing on Xilinx Spartan 3E FPGA. I've completed the design, compiled it, then tested it and everything is OK. When I started writing the final results to my boss I encountered unusual problem. The percentage of LUT consumed by the design is 123% (5734 out of 4656). How is that possible? Again everything is working fine but how come the FPGA compiler reports that 123% of the LUT is used ?! Where did (5734-4656 =  1078) LUT come from?. Compilation report is attached. Thanks in advance.

[Pcorcs]

Hello,

As FPGAs are very flexible tools, additional resources on the FPGA that are not directly utilized may be reallocated to support specified functionality. Ergo, you design calls for 123% of preallocated LUTs; however, may not be using all available Slices or Flip-Flops. These resources may be reallocated to expand the necessary LUT functionality to support the program features. 

 

In additional, the compilation will continually work to optimize FPGA resources by analyzing related logic. It will attempt to mitigate situations in which multiple program functions utilize the same set of resources; such that, the design does not unnecessarily inflate device utilization. 

Hope this helps. Please post back any further questions.

Cheers!

[Donovan_B]

This was reported to R&D (# 177016) for further investigation.  The report parser switches the numbers for LUTs and SLICEs.  The Xilinx log should show the actual usage and it will be less than 100%.  The bitfile is still valid and the design will actually fit unless the report specifically says that the compilation failed.

[Bluesky96]

Hi, thank you Pcorcs and Donovan for your response

Pcorcs. So, just to be sure I understood correctly, you're saying that the FPGA containes more than 4656 LUT but these additional resources are not utilized until the design consumes all standard 4656 LUT indicated in the report. Is that correct?

Donovan about your response. How does that fit with what Pcorcs said?

I'm sorry if I'm asking a lot of questions. That's because I need to write a report about it to my boss who is going to present it to aboard of 7 college professors. So any misunderstanding will result in kicking me off the team.

[Pcorcs]

Due to a problem the compilation report parser, the summary displays 123%. As shown in the above picture, the actual LUT utilization is at 60%. This value should be consistent with the Xflow.log file generated by the Xlinx compiler. You may find the detailed Xflow.log file in the following location, for verification:

C:\NIFPGA[Version]\srvrTmp\localhost\[Your Bitfile Compilation]

Please don't hesitate to post any further questions.

Thanks,