Question about cRIO 9004 resources about Look up table and ANALOG IO, DIGITAL IO

[TCPIP]

I have construct 2 LUTs with size 256 bytes (150 elements) each in LUT inside the while loop.

And I also used some 2 analog outputs and 2 digital outputs in a while loop and, 3 digital inputs inside the timed loop.

And it displayed that there is a shortage of the FPGA resources.

  Before adding those, the code already consumes 99% of slices of the FPGA. I suppose the FPGA will automatically optimise the resoureces of the slices to make it <100%.

  However, this time, the limitation is not due to slices, it is mainly due to the number 4 LUTs. In the compliation report, it shows that there is a little bit overuse of the number 4 LUTs..

  Can I solve the problems by reducing the half of the size of the LUT?

[MeghanK]

I am assuming that you are using arrays or clusters on your LabVIEW FPGA front panel.  Instead of reducing the size of your lookup tables, a better option might be to handshake your array data one value at a time.  This Developer Zone article will explain how to set this up.  This technique will increase your performance and reduce your gate usage.  Please let me know if you have any questions or concerns, thanks!