RT target only runs when I reconfigure the 'Open FPGA VI Reference'

[wsimpson0050]

I have a FPGA code and an RT code. The RT code is meant to capture analog input data when the 'Wait on IRQ' Timeout = False. The problem is the RT target only runs successfully when I reconfigure the 'Open FPGA VI Reference' but when I try to run it again, the RT target does not run successfully until I reconfigure the Reference again (in any way whether it is changing the OPEN from Bitfile to VI or Run Dynamically or even RUN FPGA). When I observe the issue using the "Highlight Execution' it shows that the 'Wait on IRQ' Timeout = True and continues to wait for IRQ. It should be noted that this operation is meant to run headless on Startup.

RT

FPGA

[Jacobson]

My first guess would be that in subsequent runs, the FPGA is already running and past the point where it sends the IRQ. If I'm not loading the FPGA into flash, I'll typically run the download method explicitly between open and run methods so I always know what state the FPGA is in during initialization.

[wsimpson0050]

Thank you, I believe you are correct. I made a few changes...

FPGA:

1.) I made controls on the FPGA that are controlled by the RT target. 

RT: 

2.) I made this controls and added a "reinitialize to default value". 

I did a test where I ran the FPGA first and then ran the RT Target and observed the front panels of both the RT and FPGA. The test showed that on the first run the FPGA was using the correct values from the RT target and the IRQ was being acknowledged. On the second test I would run it again but the FPGA was using the values from the previous test and not acknowledging the IRQ. To fix this I would have to 'Reinitialize all values to default" on both the FPGA and RT targets before running the test again. 

I think you may have answered the follow up question but need more understating.

How can I reinitialize the values to default on the FPGA side after starting, stopping, and starting the RT target? 

Thanks.

[wsimpson0050]

here is the ZIP file for the current setup 

[Jacobson]

There's a Reset method you can run using the FPGA reference which reverts most things to default (I think the exception is memory items). The Download method is what I normally use during initialization as it should download the target bitfile onto the FPGA regardless of what's currently on the FPGA.

If you use the Reset command, just be aware that you'll have to call the run method because the reset method will stop what's on the FPGA but won't start it up again.

[wsimpson0050]

okay thank you again. another thing, I plan on making 30-minute files that start at a 30-minute mark in time (example, start at 11:00 or 11:30). Let's say we start a file at 11:00, record for 30 minutes stop file (11:30), save it, and then start over again by 11:30. what is the best way to do this?

[Jacobson]

I think this package may already have a function to do that if you want to give it a try.

https://www.vipm.io/package/hooovahh_tremendous_tdms/

For a simple implementation, instead of directly calling a write method you could first check the current time against the time the file was created. If the file isn't 30 minutes old then you just write the data to that file. If the file is older than 30 minutes you close the existing file, create a new one, write the data to that file and pass out that new file reference for future use.