Receiving only 0s from fifo read

[BryanHunter]

I can only get 0s when i do a fifo read, but when i use scan interface mode to just get a singular value i get what i expect.  Is this a simple mistake anyone knows how to fix?

[10Degree]

This is a somewhat vague question.  You are talking about reading a FIFO that is being populated from an FPGA.  If you are able to read out zero's when using the FIFO.Read method without a timeout condition, then you are reading the data that was placed into the FIFO by the FPGA vi.  In other words, it sounds like your FPGA vi is packing the FIFO with zero's.  Start debugging there.

-cb

[BryanHunter]

Does anything look wrong with this?  The FIFO is a I32 fifo with 32767 elements

[BryanHunter]

I've also tried it converting number to boolean, then boolean to number and used a U32 FIFO, but still all zeros immediately out of the Data side on the Host.  I'm compiling it now to see if i get a 0 immediately out of the module input.

[10Degree]

The only thing that looks odd is your use of the "Loop Timer" vi to wait before the acquisition.  Change it to a "Wait" vi to implement your delay.

[BryanHunter]

I changed it to a Wait and the same thing happened.  I added an indicator straight out of the module node, and it is reading 0 also.  But when i use scan interface mode, the same module node gives me the correct reading.  Maybe the FIFO isn't the problem, but has anyone had an error where nothing but 0 is being read from the module?

[10Degree]

Sorry I have not been much help!  I don't think the fifo is the issue as you are able to read out data that the fpga has packed in.  There must be a setup or configuration step for the modules that you are missing.

[Hueter]

The method you are using looks good so far so lets dig in a little deeper.

What FPGA target are you using?

Could you post a screenshot of your LabVIEW project Window?

Could you post a screenshot with the code you are using to read the FIFO on the Host VI?

Is there a particular reason you want to conver the data to I32 before sending it in the FIFO?

-Hunter

[BryanHunter]

i believe i figured it out.  Apparently I just had to add the the module start nodes to the FPGA VI.  Here is the link to the post that helped me 

http://forums.ni.com/t5/Real-Time-Measurement-and/Error-acquiring-data-on-NI-9233/m-p/762864?query.i....

I'm casting them before i put them in the FIFO because the modules have different FXP representations.  By casting them, i can cast them back to each of their own FXP representations.  If i made a FXP FIFO, i would only have one FXP representation option, i believe.

Thanks for the help guys