Reducing resource usage on my FPGA

[Shiv0921]

Apologies it's taken me so long to respond. There hasn't been a clear cut answer to this but disabling sections of code was useful advice as I did find the main LUT eaters.

Namely some old subVIs which are liberal in the use of quotient and remainder. Also cutting out some of the decision making in the code and finding a way to use I16s rather than I32s for our data have all helped a lot. Surprisingly keeping the separate pipelined loops does come out less resource intensive, but this is for the code that can't go in SCTLS eg PID code, filtering code. 

Thanks for pointing me to it not being the front panel elements as I was about to embark on changing that and it would have been all work down the wrong route.

[wiebe@CARYA]

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@Shiv0921 wrote:

Namely some old subVIs which are liberal in the use of quotient and remainder.

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Those Q&R's are a known no-no on FPGA. Not sure why, I think there are ways to program them without a loop (which IIRC is the problem with them)