Hello Alann,
Did you get a chance to look into the FPGA and Host VIs for the examples in the FPGA RF Communications Library to see how they work? If you go to the FPGA RF Communications Library download page and download and install the library, you should be able to find the example VIs, in the following location C:\Program Files\National Instruments\LabVIEW 8.6\examples\RF Fixed Point... then you can dive deeper depending on what platform you are going to be working with. For the best support on the way this IP is implemented your best bet would probably be to post a comment on the FPGA RF Communications Library 2.1.0 page or the Reed-Solomon Decoder page, but I will provide my thoughts on the matter and hopefully it can spark some ideas.
I was looking at the example for the NI-5641R to see just how this code is implemented. The way that the code is currently working, is that the HOST VI is creating some bitstream with errors that it passes through a DMA FIFO to the FPGA (differences on HOST depending on device) and then on the FPGA VI, the code runs through the bitstream that was passed from the host and runs it through a packaged Reed-Solomon Decoding subVI.
So, if you have your data to generate that conforms to the CCSDS protocol. What I think you'll have to do is to take your Transfer Frame and pass them through the Reed-Solomon Encoder VI to create an encoded Transfer Frame. Then you could append your Transfer Header with the Frame Information and synch bits to the beginning of your encoded Transfer Frame. Once this is done, you should be able to use your modulation scheme of choice to generate the signal.
Now, on the acquisition side, you will have to bring that signal down and demodulated it, which should produce a sequence of CCSDS packets whose Transfer Frames are encoded using the R-S encoding. Now, on the FPGA, you should be able to discover the Transfer Header and extract any necessary information from it. Once you know how many bits of the Transfer Frame to use you can then process them using the R-S Decoding VI that is in the FPGA VI of the example VIs that install with the library.
For an example on how to implement some of the modulation techniques in FPGA you can check out the posted IP at the IP Corner as well as on the community for AM Modulation with FPGA.
This is my two cents on the matter, so I hope it helps.
Chris W
