Refilling Host to Target DMA FIFO on cRIO

[Cvok]

Hello, 

I need help with Host to Target DMA FIFO. Currently I'm using a flat sequence and in one frame I read data from file and fill the H2T FIFO with it ( it represents a reference for PID controller). Another frame contains a timed loop in which I control when the FIFO is read from FPGA side. Once I'm done with the routine I restart the program. What I would like to know and do is: upon finishing the routine with read reference I would like to read another file and fill the FIFO with that data to be ready to get read on FPGA without restarting the program. I believe that a parallel while loop with a case structure would suffice, does anyone have experience with such problem / or a suggestion?

Thank you in advance, if you need a part of code please PM me. 
Good day.

[CoastalMaineBird]

It seems like you've described exactly what you need to do, but can't make a connection to coding it.

What I do is write it out in pseudo-code like this:

FileNames[ ] = [ " File1.dat", "File2.dat", "File3.dat" ]

for i = 0 to NFiles - 1      { FOR loop }

    DataPoints[ ] = Read File (FileNames[i])           { read one file }

    for j = 0 to NPointsInThisFile - 1     { FOR loop }

         Put DataPoints[j] into FIFO

         wait X mSec, or wait until feedback, or whatever.

That's it, unless I've completely misunderstood you.

REPEAT    [ While loop]

[Terry_ALE]

I think you should use something more structured such as a producer consumer design patter http://www.ni.com/white-paper/3023/en/

The producer loop can read the files and the consumer loop can send the data to the FIFO.

[Cvok]

You are right in saying that I do now know how to reproduce code for my idea since I'm kind of new to LabVIEW (6 months of experience so far). Also this is my first time using DMA for sending to target. The thing is that I do not have Nfiles. I have e.g. 4 files but they could be loaded 1-3-4-2-2-3-1.. and so on, so I do not think that a for loop would do. I agree with placing it in a while loop, in a sort of producer-consumer manner ( meaning that a "flag" could be used to trigger refilling?); do you know how long does it take to write say 10000x3 array in a FIFO? 

Thank you for replies!

[Terry_ALE]

30k elements should be pretty quick for a DMA FIFO, I'd say less than a second but better to check the status of the FIFO before writing; this way it should always run at the optimal rate.

In the producer loop you could check the DMA FIFO status (number of elements) by writing nothing to the FIFO and just checking the "Empty Elements Remaining" output of the "FIFO.Write (Invoke Method)" function (on the Host) http://zone.ni.com/reference/en-XX/help/371599M-01/lvfpgahost/fpga_method_fifo_write/.  If the amount of Empty Elements Remaining is greater than the amount to write, then you can write (else, don't write).

[Cvok]

So should I write some wait for this loop or leave it to run as fast as possible? Attached is my proposed while loop according to your opinions, false case just passes the wires directly.  Would this design work in your opinion? The "Flag/Trigger" will be a local variable from a timed loop and "aR" array must be written in.

[Terry_ALE]

You could hardwire a wait if you do not expect this to change.

I prefer something more dynamic but the above may get you functional sooner.

[Cvok]

Update on this. The proposed code was modified, everything after first invoke was placed in case structure. It worked for smaller files , but a large file (100 000 points in array) "ate" entire processor time (I lost communication with cRIO). What I did next, when I realized that reading from .txt file requires a lot of resources , was placing that in a frame of a flat sequence before writing to DMA FIFO and using array indicator to store read data and using local variable of that indicator to write into DMA. Is there a better practice for doing it? Something like reading all files (e.g. 10 files), storing data in an array and then indexing this big array to get out wanted subarrays which are to be written into DMA? Thank you for replies!

[Terry_ALE]

The sequence structure and local variable do not sound like a good idea.  Local variables make memory copies and I am not sure what this buys you; could you post the new code?

If you lost communication, maybe the FPGA has not finished processing the data.  The write to FIFO function outputs "Empty Elements Remaining". If this is zero then it will wait until there is room or timeout elapses.

When dealing with larger amounts of data it is good to stage the data as it comes in.  Any luck with the producer consumer?  This uses LabVIEW Queues to buffer data from one loop to another and is very efficient.

[Cvok]

FIFO is big enough, with Configure method I set the size of FIFO to be equal to array size + 1. 

I've attached the current code which I'm testing on Windows right now. Basically I have N number of files (e.g. 10) which do not change, and I need the data from 1 file at a time to be written to FIFO and read at FPGA. Because of problems given by last code with losing communication while handling large data I have moved the reading from file part in a Frame before the "main timed loop" (produces "ucitaj" boolean which triggers writing to FIFO).  I've placed this code in a For loop to read all files and store data in Array1 which is then wired into the next Frame. Next Frame contains main timed loop(not shown) and a parallel while loop with Case structure (fig. 2) which indexes a subarray from Array1 (each file represents 1 row), and passes the subarray to the FIFO write then FIFO is empty (Empty elements remaining greater than..  & "ucitaj" = T). What are the timing limitations of this design? I've placed wait to be sure that the code is executed, because I believe that large files need more time to be read, stored in array and be read again?