Rio File Write Loop Delays - please help

[Dhasa]

Hi everyone,

I am writing data being collected from all 32 channels of a 9205 module to the onboard memory of a Rio-9074.  This is not the final requirement of the application, but it is the simplest first step.  Both the FPGA Vi and the Host Vi are attached to this post.  

Writing to the file occurs in the interior while loop, while the exterior while loop segments the files every so often (this segmentation is a requirement of our application).  I have attached a sample output file to this post as well (the output file opens well in wordpad). 

In the output file, the second and third column is a time stamp with fractional seconds.  The period of execution is 5Hz, but  If you see the first few lines in the output file, you will notice that it sometimes skips a loop iteration - the timestamp jumping from 0.6s to 1s instead of 0.6s to 0.8s.  This happens regularly throughout the file.  Any idea if this because of a physical limitation of the hardware, or the clock, or if it is because of something in my program?  If you could please take a look at my program, and help me optimize my Vis or give me suggestions on why this delay is happening, I would really appreciate it.  Please let me know if you have more questions too, and I will answer them immediately.  Thank you!

P.S - Writing to a SD card on a 9802 using these programs also causes the same problem.

[Charlie_P]

Hello Dhasa,

A few things...

1)  You have file I/O in a timed loop.  This is not a good method of file I/O.  Generally, one would use an RT FIFO in the acquisition loop and read the values out in a loop running in parallel.  Write to file in the second loop.

A second method which will help your VI's performance, though not technically "correct", is to move the Open/Create/Replace File VI outside of the loop and continue to write inside of the loop.  Again, this is NOT correct programming, but it will be better than it currently is.

2)  Your current code is such that the outer loop will only run once.  Your code will execute the same way if you simply remove the While Loop.

3)  I quickly looked through the .rtf and I only see one 0.6 increment from row 0 to row 1; all of the rest are at 0.2 increments. At what times in this file do you see skipped steps?

[Dhasa]

Hi Charlie, 

1) Could you point me to an example for this please? I don't understand how to do what you have suggested.   Should I have a timed loop to read the channels and then use this RT FIFO to write those values in a separate loop running in parallel?  I would really appreciate an example, or a quick Vi because I think this might really help me. 

2) Actually, my outer while loop runs continuously. Each time it runs, a new file is created with an incremented file name.  Segmenting files was a requirement of our application. 

3) The incorrect increments in the output files are sporadic and happen randomly, skipping a data point throughout a file in some instances.  There doesn't seem to be any order.  The skips seem to be more frequent when I try concurrently writing data to a SD card as well.

Thank you so much for your help! Please tell me what would be the best way to read and write data in point 1) 

[Charlie_P · Accepted solution]

Good Afternoon Dhasa,

The following link describes the RT FIFO that I mentioned in my previous post.  This is the method that you will want to follow to get the data from your RT host to your PC so that you can log data on the PC.  This is a preferred method (when it is an option) because of the increased storage capacity of a PC (usually) and the processing requirement to write to file on the RT host.

Real-Time FIFO for Deterministic Data Transfer Between VIs

     http://zone.ni.com/devzone/cda/tut/p/id/3934

Alternatively, you can use something more similar to the "RT FIFO Communication.lvproj" example, found by searching for FIFO in the NI Example Finder, to log on the RT host.  Keep in mind that you will want to modify this example; you do not want to write to file in a timed loop because your harddrive / flash memory access is not deterministic.

[Siamak]

Hi, it seems quite straight forward, and I checked out the example you pointed at, but still on mine they don't behave. the liitle difference on my VIs is through the main VI, I am using Invoke Node: Invoke method RUN VI to run the subVI. the main VI creates the RT FIFO and passes its name to the subVI which obtains the same RT FIFO by name (again using create module) and writes in it. Main VI, later on obtains RT FIFO in another loop (by name) and reads, but can not actually read (the read value is then reflected in a table, and is not as expected).

I have a multiple run of the same subVI from the main VI, as for a dynamic range of variables.

any ideas? my LV is 8.5 and my RT FIFO icons look a bit different, which I don't imagine can be the cause. main VI and all subVIs are in the same project, and I can ensure they actually run.

[Jon_S.]

Hello Siamak,

Can you post a portion of your code that is using the RT FIFOs?  I think I have a general idea about what you are trying to do but I want to make sure.  Also, is there a reason you are calling your subVI dynamically (VI Server) rather than statically?

[Siamak]

Hi, and thanks for the reply, however, for the time being I have got rid of the RT FIFOs and am doing another approach via shared variables,

dynamically or programmatically calling multiple of the same subVI comes from my application needs to be configurable at the beginning of run time to set a number of inputs for data acquisition,

Now on my shared variable approach (I am discussing this issue in a different thread) I am facing error on the access to the defined variables, on the main VI a number of SVs are dynamically defined at run time, on the subVIs they are to be written via DataSocket providing the URL, and the main VI should read them again via DataSocket and URL of the SV, still the read is giving Generic Error,...

Siamak