Running multiple FPGA references on a CompactRIO

[rbardsley]

Hello,

I am trying to run multiple FPGA references to multiple VIs on my FPGA without any luck. We are developing a very complex system and I am trying to keep it as compartmentalized as possible, especially as we have several developers working in parallel.

I would like to have 1 VI running on the FPGA to control a series of LEDs. I would also like to have a separate VI dedicated to controlling several solenoid valves. (this is a simplification of what we are doing) In my LabView code I have connected 2 FPGA references to 2 unique FPGA read/write controls, 1 pointing to the LED VI, the other to the solenoid VI. When I do this, only the first VI seems to work. Depending on how I have it configured, all of my RT loops seem to break.

Can LabView support running multiple FPGA VI references at the same time?

I can't find any documentation on how to do this better. I am trying to avoid having to lump everything into a single FPGA VI.

Thanks for your advice,

Ryan Bardsley

[MehakD]

Ryan,

LabVIEW does not support running more than 1 FPGA VI on the FPGA. However what you can do is use both the VIs as subVIs in a top level VI.

I hope this helps!

[The Specialist]

Hi Ryan,

I wanted to try that once before as well.  I think it is a limitation of of only being able to run one bitfile at a time.  It would be cool though...wink wink.  I am not really sure how it would work though, since I believe most FPGA devices can only hadle one bitfile at a time.  If I were you this is what I would do.

Start with a top-level VI like Mehak said.  Lay down your 2 subsystems like subVIs.  Then attach all the inputs and ouputs to each individual subsystem.  Then compile the VI.  I know it is kind of a cheap workaround, but you can still have you developers individually work on there own portions without effecting the opposite VI.  You can also let them both have their own DMA to get the information back to the host without interfering with each other.  Plus since everything on a FPGA runs in true hardware parallel your not eating up each others CPU or anything. 

On the host side you will only have one FPGA reference, but then it splits so that two different parts of the of the FPGAs code are being used in two different parts of the RT code.  That seems like the best way to separate the system without losing too much resources.