SPI Frame Timing Reliability

[johnsoja]

I have retargeted the CRIO SPI example that communicates with an Analog Devices ADIS16350 inertial measurement unit to my PXI-7813R FPGA module and it functions as designed.  The fact that so much of the implementation is performed at the "host" level results in having no reliability in the frame timing.  In other words, I need to poll the device on a regular cycle (500Hz, 1000Hz, etc.) that is repeatable.  Of course, since the SPI writes are initiated by the host (PC), this frame timing is very sloppy.  I would like to control the frame timing at the FPGA level, so as to have repeatable acquisition timing.  Has anyone modified this example or any other SPI based project to accomplish what I'm describing?  If so, can you provide the code and/or give me any pointers on what are the key mods required to do this?

Thanks,

Joel J.

[johnsoja]

This is the link to the SPI example that I'm using.

http://zone.ni.com/devzone/cda/epd/p/id/6264

---

@johnsoja wrote:

I have retargeted the CRIO SPI example that communicates with an Analog Devices ADIS16350 inertial measurement unit to my PXI-7813R FPGA module and it functions as designed.  The fact that so much of the implementation is performed at the "host" level results in having no reliability in the frame timing.  In other words, I need to poll the device on a regular cycle (500Hz, 1000Hz, etc.) that is repeatable.  Of course, since the SPI writes are initiated by the host (PC), this frame timing is very sloppy.  I would like to control the frame timing at the FPGA level, so as to have repeatable acquisition timing.  Has anyone modified this example or any other SPI based project to accomplish what I'm describing?  If so, can you provide the code and/or give me any pointers on what are the key mods required to do this?

Thanks,

Joel J.

---