02-07-2018 04:08 PM
I wrote code a few weeks ago using this library that re-configures the number of bits (although I only use full bytes) and it works fine. Can you share your code?
02-07-2018 04:36 PM
This is the code:
I send two bytes: xC0 xC0 Followed by seven bytes x02 x28 x87 xFA x00 x00 x00
I want CS reset high between the two sequences
I obtain the first frame OK
the second frame is truncated at 2 bytes x02 x28
In fact it is truncated at the length secified in the first configuration VI
Thanks for your help
Best regards
Thierry
02-08-2018 01:46 AM - edited 02-08-2018 01:46 AM
Hi Thierry,
The API consists of FPGA VI´s and RT VI´s.
Open a new VI in FPGA. Go to Connectivity -> SPI -> SPI Engine. Place it in your VI. Configure your SPI FPGA IO and compile it.
Then open a new VI in RT. In your case, the RT VI could look like in the picture I uploaded.
Regards,
GM_1
02-10-2018 04:20 PM
Hi GM_1
I have tested this solution; It works, but the problem is that I have 12 ms between the two sequences (frame C0, C0 and frame 02, 28, 87, FA, 0, 0, 0)
This delay is absolutly unacceptable in my application and I have no idea of the reason of this delay
It is the reason why I was trying to make all the sequence inside the FPGA
Any idea of the reason of this delay?
Thanks
Best regards
Thierry
02-11-2018 12:01 PM
SOLVED!!
The only thing to do was to introduce a small delay (few µs) before a re-configure, doing this it is taken into account
Thanks to GM_1 and Nathand for their help
Best regards
Thierry