The problem with sample clock is that it is always running. What I did in the past was to create my own SCLK, SDO, and CS as follows:
Bit 0 is dedicated to SCLK, Bit 1 to SDO, Bit 2 to CS, and Bit 3 to a flag (I'll explain later). Use a 1D array to hold the data that you will write to the DIO port. Lets say you want to write 10101010 to the SDO line. Form you array like this:
Bit 0 ---> Bit 3 (SCLK, SDO, CS, Flag)
0000 - sets CS low
0100 - sets the first SDO bit
1100 - clocks the first SDO bit
0000 - clock low, set next SDO bit
1000 - clock the next SDO bit
0100 - clock low, set next SDO bit
1100 - clock the next SDO bit
0000 - clock low, set next SDO bit
continue on until all SDO bits have been clocked.
Now to read SDI:
1001 - clock high causes device to send SDI, also set flag bit high
0001 - clock low
continue on until 8 clocks have been sent.
Now take your read buffer and extract only the lines where the flag bit is high. This gives the data returned from the device.
Of course this will reduce your SCLK rate to half the sample clock rate. So set you sample clock to twice the frequency of your intended SCLK rate.
There are SPI cases where you can send data and receive data at the same time. Send command 1, then send command 2 and receive response 1 at the same time. If you use this scheme, you don't need the flag bit. Just ignore the first byte you receive. Also, if you use this scheme, you can invert the SCLK bit to clock on the negative edge.
I hope this all makes sense.
