Setting Timed Loop Period on Xilinx Spartan 3E FPGA Targets

[adecold]

I have a spartan 3E FPGA target that i am currently using for my senior design project. I'm trying to display some images through the VGA port on the board but i am getting timing issues with the board.

First of all, the VGA examples that came with the board driver do NOT work. My monitor displays an out of range error and displays that the frequency is twice the range that it should be. Changing the period on the timed loops makes no difference, regardless of how ridiculous they are. When i create a new timed loop, it doesn't allow me specify the period. In fact the only inputs to the timed loop is the clock source and error in.

Is this a bug in the software and how can if fix this issue? (The issue is displaying anything via VGA)

Tutu

PS. the ONLY things installed are 

LabVIEW 8.5.1 + LV FPGA + Xilinx XUP drivers 

The screen shots attached shows two timed loops... the one above is a new timed loop created from the block pallete while the one below is what was in the example. Notice how the newly created one cannot be expanded to allow more inputs and also how the old one has so many (including processor and other inputs that would be more appropriate for an RT target). 

[Wiebe@CARYA]

You should not be able to set the period. If you set it (you can by copy
pasting, or by creating atimed loop in another target, and load the vi on
FPGA), the period will be ignored.

The timed loop was designed for real time targets, so I have no clue why
this isn't possible to set the period on FPGA's.

The main use for the timed loop is the single cycled timed loop (SCTL),
which has a special meaning. Everything in the SCTL will be optimised for
speed...

I don't know why the examples don't work (could be anything), but I would
look at the frequency of the board. You should be able to set it to several
frequencies (the other fgpa targets can do that anyway). Right clicking in
your project on the FPGA item should allow you to change the frequency.
Setting the timed loop period don't help.

Regards,

Wiebe.

[adecold]

The board only has one onboard 50MHz clock and i am trying to divide it to achieve a 25Mhz timed loop. It does have pins for an external clock but its crunch time on the project and delivery will take to long. The clock on the FPGA (in the project) doesn't look like it can be changed.

I was trying to do a 50Mhz timed sequence in order to achieve the desired frequency but the timed sequence is "not supported" on that target.

Still searching ideas..

Thanks

[Wiebe@CARYA]

I was refering to the derived clocks...

It's not that hard to make a SCTL skip frames. Normally' you don't want to
use cases on FPGA, but in this case you could use it. Wrap a case around the
code inside the SCTL. Make a shift register. Make one case (with the code in
it) case x (a number), the other one default. In the default case, add one
to the value in the shift register, in the x case, put it back to 0. Now the
code will be executed once in x times...

Not sure if this is helpful for getting the example working. It is designed
for your board, and if it doesn't work, the code is probably not the
problem.

You should try the code with the oldest monitor (not lcd, but an old
fasioned crt) you can find. The new monitor is probably not VGA, but SVGA,
and who knows what it expects. There are embedded devices that have the same
problem, perhaps for the same reason.

Regards,

Wiebe.

[Spectre_Dave]

You could use the Loop Timer function to set the loop time.  Setting the counter units to two (2) ticks should slow the loop down by a factor of two.

The function is  in the timing palette.

[adecold]

@Wiebe

Target doesn't support derived clocks, but the case structure seemed to fixed it. A rather crude method but fixed it good. I am testing with 2 LCDs and i think i prefer them because they actually tell me the frequencies even when it doesn't display so i know what to tweak. The example code for VGA on the 8.5 & 8.6 beta drivers do NOT run out of the box without modifying the timed loop.

@VADave

I tried that already but i think the some timing or the execution of code becomes undeterministic. Tried the timed loop, didn't work. Then tried the wait, that didn't work. In fact i got worse results because the monitors could not even identify any frequencies and would just fail to display. And i did put them in Flat Sequence Structures.

Thanks all

[Wiebe@CARYA]

"adecold" <x@no.email> wrote in message
news:1227564606707-814111@exchange.ni.com...
> @ Wiebe&nbsp;Target doesn't support derived clocks, but the case structure
seemed to fixed it. A rather crude method but fixed it good. I am testing
with 2 LCDs and i think i prefer them because they actually tell me the
frequencies even when it doesn't display so i know what to tweak. The
example code for VGA on the 8.5 &amp; 8.6 beta drivers do NOT run out of the
box without modifying the timed loop.

Do you mean that you've got it working now? Could you share the details of
the modifications of the timed loop? Perhaps you could post your code here
if it works. I don't need it, but it will complete this thread.

Regards,

Wiebe.