Shared Variables not working under FPGA interface??

[charmand79]

Hi all

I have a cRIO 9074 controller with 9074 chassis.

I defined a number of shared variables under my RIO controller and written a user-interface VI in my host PC, where I feed some network shared variables into RIO and getting some other back from RIO to my host front panel. Naturally, the VI dealing with writing/reading the network variable data to/from the actual I/O channels is under my RIO controller.

The problem is that although it all seems to be working fine when my RIO is set to Scan engine interface, the same VIs give the following error when I switch my RIO to FPGA interface support.

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Possible reason(s):

CompactRIO:  (Hex 0xFFFF0000) Unable to communicate with the module. Reinsert the module and check connections. If the chassis is in FPGA Interface programming mode, make sure you have opened an FPGA reference to a bitfile or FPGA VI with Scan Interface support for the module you are trying to access using the Scan Interface.

This error or warning occurred while writing the following Shared Variable:
\\AMR-cRIO9074\B1-DO\JCV1_C1_B1
\\160.40.15.231\B1-DO\JCV1_C1_B1

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Note that I get this error message for each I/O channel I am calling on my RIO. Also note that there is still no FPGA reference currently in any of the VIs involved.. The reason I want to solve the problem is because later on I will have to add some FPGA in my code, so I cannot just switch my RIO to scan interface..

Any help would be much appreciated,

harry

[dkfire · Accepted solution]

When you disable the Scan Engine on the cRIO platform, you need to have some FPGA code runing.

There are noway that your controller knows about any module, and it can't read anything from any module.

If you do not have a FPGA vi that is sending values from a module port to your controller, you need to have Scan Engine enabled.

The error message clearly state that you need to have an open FPGA vi reference or Scan Engine to be able to read values from and to a module.

You are able to have both the Scan Engine and a custom FPGA code runing at the same time on a FPGA. 

Is there a reason for you not to run with the Scan Engine ?

[charmand79]

Hi dkfire,

thanks for another reply.. I tried your suggestion but I still get the same error message. What I did is I opened a reference to a compiled fpga vi at the start of my code but no luck. I ll try some more combinations on this track. Please note that I must have scan engne and fpga running together because I will have both types of hardware interface on my final vi. Also, maybe I am being confused with your term "disable the scan engine" but I havent actually disabled it. I have just used the Labview FPGA interface in the programming mode option, but still scan engine is running concurrently...

Cheers,

Harry

[dkfire]

Ok, so you are running i hybrid mode. ( You are able also to run without Scan Engine, that's why I say disable 🙂 )

If you can, please post your code, so that I can see what you are doing.

Opening a reference to a FPGA is not enough, unless you have defined some user variables.

http://zone.ni.com/reference/en-XX/help/371361F-01/lvioscanhelp/io_vars/

There is also the possibility of using the Front Panel controls and indicators for the VI for the FPGA.

In this option, you need the reference and a Read/Write Control to interact with the Front Panel.

Hope I made some sense 😉

[charmand79]

Hi,

OK, so you were right.. Opening and closing an FPGA reference solved the problem.. The reason it did not work the first time I tried it is because I was opening and closing the FPGA inside the VI running in cRIO, whereas it seems I should be doing that in the host PC vi... Doing the latter solved the problem..

Thanks a lot dkfire

[dkfire]

I would suggest to open the FPGA reference i your cRIO application, NOT on a VI running on a host PC.

There must be something in the cRIO code that makes this fault.

If you are able to post your code, I can take a look at it.   

[charmand79]

dkfire,

it seems that you bring the best out of me... I re-checked my RIO VI and realised that I was stupid enough not to put my close FPGA inside a case structure, which practically meant that I was opening AND closing my FPGA reference on the first iteration...

Thanks a lot, again... Next time I ll try to be more careful..