Simulating LabVIEW FPGA code on PC - problem with timing

[Sina_RM]

Hello everyone

I am quite new to LabVIEW and LabVIEW FPGA.

I want to use NI Compact RIO – 9114 (40 MHz clock rate) to control an Modular Multilevel Converter (MMC).

For preliminary experiments, I want to create two triangular waveforms (with frequency of 1 kHz) with 180 degrees phase shift, to implement SPWM. The triangular waveform is between 0 and +1.

I am using a modified version of “[FPGA] FXPT TriangleGen (use inside SCTL).vi” (My VIs have been attached).

              1- Is there any way to see the exact produced waveforms on PC or Real Time target?

               I have tried simulated I/O mode, and tried to use waveform chart.

               I have also tried to simulate the VI in My Computer (PC host?) and used waveform graph.

               However, I have problem with timing. I can’t understand how to relate real time, the time that FPGA                 needs to run the program and give the waveform samples, and simulated time on PC, in the above                 environments.

               Could you please suggest me a way to test my waveforms before compiling the code on the FPGA                 board?

              2- How can I adjust the x-axis of waveform chart and waveform graph to be compatible with real                      time? I need to do this to see whether the frequency and phase shift between the waveforms are                    implemented correctly or not.

              3- As “discrete delay function” can produce limited delay, is there any alternative way to produce                      phase shift between the waveforms (instead of connecting more discrete delay function in series)?

              4- Are there any suggested references or tutorials for learning basics of LabVIEW FPGA and                          LabVIEW Real-Time for power electronic applications?

Thank you in advance. Answer to any of the above questions can help me a lot and is really appreciated.

Best regards,

Sina

[Bob_Schor]

It would be so much easier to understand (and, possibly even test,) your code if you compressed the folder containing the Project (including the .lvproj file) and attached the resulting .zip file.  We'd have all of the VIs, could see all of the code, try out edits, etc.  I'll wait to see everything (so I don't have to "guess" what you are doing).

Bob Schor

[Sina_RM]

Hello Bob Schor

Thank you so much for your swift reply.

Please find the project attached.

Regards,

Sina

[Bob_Schor]

There's Bad News and Good News (that's sounds backwards, but I think you'll understand ...)

The Bad News is that I can't open your FPGA code (I probably don't have the right drivers installed).  However, a number of my colleagues who are much more savvy about cRIOs than I (I've been doing LabVIEW for a while, but have been using FPGAs for about a year), and having your code will help them to help you!  (That's the Good News).

Bob Schor

[Sina_RM]

Thanks a lot Bob, your time is really appreciated.

I am waiting to hear from other colleagues soon.

Best regards,

Sina

[StellaTeam]

Hello Sina,

I would like very much to hear the solution you found, particularly for point #3

Did anyone give you an answer on that?

Thanks, best regards,

Romain