Simulation of IQ on LabVIEW FPGA

[Vaibhav10511]

Hello, 

I am trying to write a logic for generating an simulated IQ signal, I can simulate generation of real and imaginary signal but unlike host VIs, but I haven't been able to find a way in FPGA  to create a complex signal from real and imaginary. I have been through high through complex multiply functions but, it requires 2 complex number for operation. I am looking for a way to convert the sine and cosine signal for complex signal. 

How can I implement that in FPGA ? 

[GerdW]

Hi Vaibhav,

---

@Vaibhav10511 wrote:

I am looking for a way to convert the sine and cosine signal for complex signal. 

How can I implement that in FPGA ?

---

A complex number simply is a compound of two floats (with some additional conventions about using them).

Have you tried to work with two float values in the FPGA?

[jjohn1]

It seems to me you would simply put the in phase (I) signal in the real part of a complex number and the quadrature (Q) in the imaginary part.  An array of these complex values would be the complex waveform.  The "Re/Im to Complex" VI can do this for two arrays.  Another option is to interleave the two arrays to a single array and type cast this array to a complex double array.

[Terry_ALE]

---

@Vaibhav10511 wrote:

Hello, 

I am trying to write a logic for generating an simulated IQ signal, I can simulate generation of real and imaginary signal but unlike host VIs, but I haven't been able to find a way in FPGA  to create a complex signal from real and imaginary. I have been through high through complex multiply functions but, it requires 2 complex number for operation. I am looking for a way to convert the sine and cosine signal for complex signal. 

How can I implement that in FPGA ? 

---

See https://youtu.be/vVjWFFclU6I?si=r01AAep_L9A69EXN&t=94 (roughly at 94 seconds) they show IQ data.  They use a cluster (typedef) with two fixed point values for I and Q.  See if you can find these functions.

How are you going to generate the IQ data on the FPGA?  Maybe Xilinx DDS?